L6722TR STMicroelectronics, L6722TR Datasheet - Page 18

• Manufacturer Part Number: L6722TR
• Description: IC BUCK ADJ 2A TRPL 36VFQFPN
• Manufacturer: STMicroelectronics
• Type: Step-Down (Buck)r

Specifications of L6722TR

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 3
• Voltage - Output: Adj to 0.8V
• Current - Output: 2A
• Frequency - Switching: 100kHz
• Voltage - Input: 12V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-VFQFN, 36-VFQFPN
• Power - Output: 3.5W
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5904-2

7 Output voltage positioning
Warning:
7.2
18/34
Figure 8.
●
●
●
Offset resistors may be simply defined as follow
where V
mode.
Offset current is always sourced from REF_IN pin: to avoid having steps during soft-start, the
introduction of C
the soft-start time as well as long enough to smooth the initial step. Typical values are in the
range of few tens / hundreds of nF.
Offset function can be easily disabled by shorting REF_IN and REF_OUT together.
Maximum offset must be limited to less than 200mV to avoid setting the OVP protection
resulting in a maximum +25% margin.
Droop function (optional)
This method "recovers" part of the drop due to the output capacitor ESR in the load transient,
introducing a dependence of the output voltage on the load current: a static error proportional to
the output current causes the output voltage to vary according to the sensed current.
Figure 9
flowing across the three inductors is read through the R
R
of the currents of the three phases. The current I
sourced by the FB pin (I
R
D
OS1
programs a transconductance gain and generates a current I
No Offset (M1=1; M2=0)
Positive Margin (M1=0; M2=0)
Negative Margin (M1=0; M2=1)
=
TARGET-POS
Ref
shows the Current Sense Circuit used to implement the Droop Function. The current
V
-------------------------------------------------------- -
REF_OUT
TARGET POS
Offset definition (margin mode)
M1
M2
OS
I
is required. The resulting time-constant need to be negligible with respect to
OS
–
and V
R
DROOP
OS1
–
TARGET-NEG
Ref
REF_IN
R
). R
OS2
FB
V
V
REFIN
gives the final gain to program the desired load-line slope.
REFIN
are the target voltages for positive and negative margin
C
OS
FB
R
=
=
OS2
Ref
(
Ref
CS
R
R
=
FB
F
+
is then mirrored and, multiplied by three,
+
R
I
OS
OS1
I
PH
OS
COMP
C
⋅
F
- C
⋅
⋅
R
R
OS1
PH
--------------------------------------------------------------------------------------- -
V
OS1
TARGET POS
VSEN
filter across CS+ and CS- pins.
CS
)
proportional to the average
⋅
----------------------------------- -
R
V
–
OS1
TARGET POS
64k
R
64k
R
OS2
+
1
–
(Remote Sense)
R
V
FBR
To Vout
OS2
–
TARGET NEG
R
2
FBG
L6722
–