LTC1261CS8#TRPBF Linear Technology, LTC1261CS8#TRPBF Datasheet - Page 7

IC VOLT INVERT SW-CAP ADJ 8-SOIC

LTC1261CS8#TRPBF

Manufacturer Part Number
LTC1261CS8#TRPBF
Description
IC VOLT INVERT SW-CAP ADJ 8-SOIC
Manufacturer
Linear Technology
Type
Switched Capacitor (Charge Pump), Invertingr
Datasheet

Specifications of LTC1261CS8#TRPBF

Internal Switch(s)
Yes
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
-1.25 ~ -8 V
Current - Output
15mA
Frequency - Switching
550kHz
Voltage - Input
3 ~ 8 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-

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APPLICATIONS
The output voltage is monitored by COMP1 which com-
pares a divided replica of the output at ADJ (COMP for
fixed output parts) to the internal reference. At the begin-
ning of a cycle the clock is low, forcing the output of the
AND gate low and charging the flying capacitors. The next
rising clock edge sets the RS latch, setting the charge
pump to transfer charge from the flying capacitors to the
output capacitor. As long as the output is below the set
point, COMP1 stays low, the latch stays set and the charge
pump runs at the full 50% duty cycle of the clock gated
through the AND gate. As the output approaches the set
voltage, COMP1 will trip whenever the divided signal
exceeds the internal 1.24V reference relative to OUT. This
resets the RS latch and truncates the clock pulses, reduc-
ing the amount of charge transferred to the output capaci-
tor and regulating the output voltage. If the output exceeds
the set point, COMP1 stays high, inhibiting the RS latch
and disabling the charge pump.
550kHz
CLK
S
R
U
Q
INFORMATION
U
COMP 1
V
REF
+
= 1.24V
W
60mV
1.18V
S2
V
OUT
U
S1
S3
Figure 2. Block Diagram
C1
C1
C1
+
V
CC
S4
+
COMP 2
COMP2 also monitors the divided signal at ADJ but it is
connected to a 1.18V reference, 5% below the main
reference voltage. When the divided output exceeds this
lower reference voltage indicating that the output is within
5% of the set value, COMP2 goes high turning on the REG
output transistor. This is an open drain N-channel device
capable of sinking 5mA with a 3.3V V
V
below V
damage up to a maximum of 12V above ground. Note that
the REG output only indicates if the magnitude of the
output is below the magnitude of the set point by 5% (i.e.,
V
output is forced higher than the magnitude of the set point
( i.e., to – 6V when the output is set for – 5V) the REG
output will stay low.
S5
S7
CC
OUT
C2
C2
C2
+
. When in the “off” state (divided output more than 5%
> – 4.75V for a – 5V set point). If the magnitude of the
S6
REF
) the drain can be pulled above V
124k
226k
100k
50k
*LTC1261CS14 ONLY
ADJ/COMP
R
OUT
REG
R1*
R0*
ADJ
*
+
INTERNALLY
CONNECTED FOR
FIXED OUTPUT
VOLTAGE PARTS
C
OUT
LTC1261 • F02
CC
and 8mA with a 5V
LTC1261
CC
without
7

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