IC CTRLR PWM 1PHASE SO-8

L6726A

Manufacturer Part NumberL6726A
DescriptionIC CTRLR PWM 1PHASE SO-8
ManufacturerSTMicroelectronics
TypeStep-Down (Buck)
L6726A datasheet
 


Specifications of L6726A

Internal Switch(s)NoSynchronous RectifierNo
Number Of Outputs1Voltage - OutputAdj to 0.8V
Frequency - Switching270kHzVoltage - Input1.5 ~ 12 V
Operating Temperature-20°C ~ 85°CMounting TypeSurface Mount
Package / Case8-SOIC (3.9mm Width)Output Current1.5 A
Input Voltage4.1 V to 13.2 VOperating Temperature Range- 40 C to + 150 C
Mounting StyleSMD/SMTFor Use With497-9046 - BOARD EVAL BASED ON L6726A497-6364 - BOARD DEMO FOR TS4995EIJT497-6259 - BOARD EVAL 1PH STPDN CONV L6726A
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Output-
Power - Output-  
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Application details
8.3
Soft-start time calculation
To calculate SS time (t
t
SS
The previous equation refers only to V
OC setting phase or COMP set free to the beginning of V
approximately estimated as follow:
t
delay
Once calculated t
output capacitor bank can be estimated:
I
startup
8.4
Layout guidelines
L6726A provides control functions and high current integrated drivers to implement high-
current step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure
10) must be a part of a power plane and anyway realized by wide and thick copper
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
Figure 10. Power connections (heavy lines)
The input capacitance (C
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper number of vias when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
18/35
), the following approximated equation can be used (C
SS
V
OUT
-------------- ΔV
C
F
OSC
V
IN
=
------------------------------------------------- -
I
SS
ramp up time. The time elapsed from the end of
OUT
C
0.8V
F
=
----------------------- -
I
SS
, also the current delivered by the converter during SS to charge the
SS
C
V
OUT
OUT
=
--------------------------------- -
t
SS
UGATE
PHASE
L6726A
LGATE
GND
), or at least a portion of the total capacitance needed, has to be
IN
Doc ID 12754 Rev 4
ramp up (see
Figure
OUT
V
IN
C
IN
L
C
OUT
LOAD
L6726A
<<C
):
P
F
6) can be