IC CTRLR PWM 1PHASE SO-8

L6726A

Manufacturer Part NumberL6726A
DescriptionIC CTRLR PWM 1PHASE SO-8
ManufacturerSTMicroelectronics
TypeStep-Down (Buck)
L6726A datasheet
 


Specifications of L6726A

Internal Switch(s)NoSynchronous RectifierNo
Number Of Outputs1Voltage - OutputAdj to 0.8V
Frequency - Switching270kHzVoltage - Input1.5 ~ 12 V
Operating Temperature-20°C ~ 85°CMounting TypeSurface Mount
Package / Case8-SOIC (3.9mm Width)Output Current1.5 A
Input Voltage4.1 V to 13.2 VOperating Temperature Range- 40 C to + 150 C
Mounting StyleSMD/SMTFor Use With497-9046 - BOARD EVAL BASED ON L6726A497-6364 - BOARD DEMO FOR TS4995EIJT497-6259 - BOARD EVAL 1PH STPDN CONV L6726A
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Output-
Power - Output-  
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Application Information
9.2
Output capacitors
Output capacitors choice depends on the application constraints in point of output voltage
ripple and output voltage deviation during a load transient.
During steady-state conditions, the output voltage ripple is influenced by ESR and
capacitance of the output capacitors as follows:
ΔV
ΔI
=
OUT_ESR
L
ΔV
ΔI
-------------------------------------- -
=
OUT_C
L
8 C
Where ΔI
is the inductor current ripple. These contribution are not in phase, so total ripple
L
will be lower than the sum of their moduli. Even ESL and board parasitic inductance can
contribute significantly to output ripple.
During a load variation, the output capacitors supply to the load the additional current or
absorb the current in excess delivered by the inductor until converter reaction is completed.
In fact, even if the controller react immediately to the load transient saturating the duty cycle
to 80% or 0%, the current slew rate is limited by the inductance. At first approximation,
output voltage drop, based on ESR and capacitor charge/discharge and considering an
ideal load-step, can be estimated as follows:
ΔV
ΔI
=
OUT_ESR
OUT
L ΔI
ΔV
=
------------------------------------- -
OUT_C
2 C
OUT
Where ΔV
is the voltage applied to the inductor during the transient (
L
the load appliance or V
MLCC capacitors typically have low ESR to minimize the ripple but also have low
capacitance that do not minimize the capacitive voltage deviation during load transient. On
the contrary, electrolytic capacitors usually have higher capacitance to minimize capacitive
voltage deviation during load transient, but also higher ESR value resulting in higher ripple
voltage and resistive voltage drop. For these reasons, a mix between electrolytic and MLCC
capacitor is usually suggested to minimize ripple as well as reducing voltage deviation in
dynamic conditions.
9.3
Input capacitors
The input capacitor bank is designed mainly to stand input rms current, which depends on
output current (I
OUT
I
I
D
=
rms
OUT
The equation reaches its maximum value, I
capacitor ESR:
2
P
=
ESR I
rms
22/35
ESR
1
F
OUT
SW
ESR
2
OUT
ΔV
L
for the load removal).
OUT
) and duty-cycle (D) for the regulation as follows:
(
)
1 D
OUT
Doc ID 12754 Rev 4
D
V
MAX
/2, when D = 0.5. Losses depend on input
L6726A
for
V
IN
OUT