L6727 STMicroelectronics, L6727 Datasheet - Page 17

IC PWM CTLR SGL PHASE SO-8

L6727

Manufacturer Part Number
L6727
Description
IC PWM CTLR SGL PHASE SO-8
Manufacturer
STMicroelectronics
Type
Step-Down (Buck)r
Datasheet

Specifications of L6727

Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
Adj to 0.8V
Frequency - Switching
300kHz
Voltage - Input
1.5 ~ 12 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Output Current
1.5 A
Input Voltage
- 0.3 V to + 15 V
Switching Frequency
300 KHz
Operating Temperature Range
- 40 C to + 150 C
Mounting Style
SMD/SMT
Duty Cycle (max)
80 %
For Use With
497-8266 - BOARD EVAL BASED ON L6727497-6258 - BOARD EVAL 1PH STPDWN CONV L6727
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output
-
Power - Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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L6727
9.3
To place the poles and zeroes of the compensation network, the following suggestions may
be followed:
Layout guidelines
L6727 provides control functions and high current integrated drivers to implement high-
current step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
The input capacitance (C
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
a)
b)
c)
d)
e)
f)
8) must be part of a power plane and anyway realized by wide and thick copper
Set the gain R
according to the approximated formula (suggested values for R
to 5 kΩ):
Place F
Place F
Place F
Check that compensation network gain is lower than open loop EA gain;
Estimate phase margin obtained (it should be greater than 45 °) and repeat,
modifying parameters, if necessary.
R
C
----------
R
C
C
S
R
S
FB
P
F
F
=
=
=
=
Z1
P1
Z2
=
-------------------------- -
----------------- - 1
2 F
------------------------------ -
π R
-----------------------------
π R
----------------------------------------------------------
2π R
F
F
------------
SW
below F
at F
at F
F
R
0dB
LC
LC
FB
S
F
1
1
F
LC
ESR
F
F
/R
IN
F
ΔV
------------------ -
SW
LC
C
), or at least a portion of the total capacitance needed, has to be
and F
FB
C
V
:
LC
F
OSC
IN
F
in order to obtain the desired closed loop regulator bandwidth
Doc ID 12933 Rev 4
F
(typically 0.5*F
ESR
P2
at half of the switching frequency:
1
LC
):
Application details
FB
range from 2 kΩ
17/34

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