L6730B STMicroelectronics, L6730B Datasheet
L6730B
Specifications of L6730B
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L6730B Summary of contents
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... Pre-bias start up capability (L6730) ■ Selectable source/sink or source only capability after soft-start (L6730) ■ Selectable constant current or hiccup mode overcurrent protection after soft-start (L6730B) ■ Power Good output with programmable delay ■ Overvoltage protection with selectable latched/not-latched mode ■ Thermal shut-down ■ ...
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... Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.8 Monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.9 Adjustable masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.10 Multifunction pin (S/O/U L6730) (CC/O/U L6730B 5.11 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.12 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.13 Minimum ON-time TON(MIN 5.14 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.14.1 5.14.2 6 Application details ...
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... L6730 - L6730B 6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.5 Two quadrant or one quadrant operation mode (L6730 L6730 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 POL demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 Revision history ...
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... A leading edge adjustable blanking time is also available to avoid false over- current-protection (OCP) intervention in every application condition possible to select the HICCUP mode or the constant current protection (L6730B) after the soft-start phase. During this phase constant current protection is provided possible to select the sink- source or the source-only mode capability (before the device powers on) by acting on a multifunction pin (L6730) ...
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... Functional description Figure 1. Block diagram PGOOD OCL Monitor SS/INH Protection and Ref SYNCH OSC EAREF PGOOD + SINK/OVP/UVLO* - MASKING TIME TMASK ADJUSTMENT Note: In the L6730B the multifunction pin is: CC/OVP/UVLO. V =4.5V to14V CC OCH VCCDR LDO OSC L6730/B - 0.6V 1.2V + PWM E COMP FB Doc ID 11938 Rev 3 ...
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... PGOOD DELAY PGdelay L6730 H_MASK H_EAREF PGOOD OSC SOU/COU TMASK THERMAL PAD EAREF L_MASK L_EAREF EAREF Doc ID 11938 Rev 3 L6730 - L6730B R FILT V = 1.8V to 14V IN R OCH OCH C OCH C V IN_BULK CCDR VCCDR R BOOT BOOT C BOOT C IN_HF R HS HGATE HS L PHASE C VCCDR ...
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... L6730 - L6730B 2 Electrical data 2.1 Maximum rating Table 2. Absolute maximum ratings Symbol BOOT - PHASE V V HGATE - PHASE V BOOT V PHASE OCH Pin PGOOD Pin OTHER PINS 2.2 Thermal data Table 3. Thermal data Symbol (1) R thJA T STG Package mounted on demonstration board Parameter V to GND and PGND, OCH, PGOOD ...
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... not used, the SYNCH pin can be left floating. With this pin it is possible: To enable-disable the sink mode current capability after SS (L6730); To enable-disable the constant current OCP after SS (L6730B); To enable-disable the latch mode for the OVP; To set the UVLO threshold for the 5 V BUS and 12 V BUS. ...
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... L6730 - L6730B Table 4. Pin connection (continued) Pin n. Name T 4 MASK 5 GND COMP 8 SS/INH 9 EAREF 10 OSC Description The user can select two different values for the leading edge blanking time on the peak overcurrent protection by connecting this pin to V GND. The device captures the analog value present at this pin at the start-up when V meets the UVLO threshold ...
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... Pull up this pin logical signal. Thermal Pad connects the silicon substrate and makes good thermal contact with the PCB. Connect to the PCB power ground plane. Doc ID 11938 Rev 3 L6730 - L6730B ) from this pin OCL ). The over-current threshold OCL ⋅ ...
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... L6730 - L6730B 4 Electrical characteristics 25°C unless otherwise specified CC A Table 5. Electrical characteristics Symbol Parameter V supply current CC V stand by current quiescent current CC Power-ON Turn-ON V threshold CC 5V BUS Turn-OFF V threshold CC Turn-ON V threshold CC 12V BUS Turn-OFF V threshold CC Turn-ON V threshold OCH Turn-OFF V OCH V regulation CCDR ...
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... V rising 0.6V EAREF V falling 0.6V EAREF V > OVP Trip OSC V rising FB V falling -5mA PGOOD Doc ID 11938 Rev 3 L6730 - L6730B Min. Typ. Max. Unit μA 0.290 0.5 2 100 dB 10 MHz 5 V/μs Ω 1.7 Ω 1.12 Ω 1.15 Ω 0.6 μA ...
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... L6730 - L6730B Table 6. Thermal characterizations (V Symbol Oscillator f Initial accuracy OSC Output voltage (1.2V MODE) V Output voltage FB Output voltage (0.6V MODE) V Output voltage Parameter Test condition OSC = OPEN 0°C~ 125° 0°C~ 125° -40°C~ 125° 0°C~ 125° -40°C~ 125°C ...
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... CCDR . − Fsw 400 KHz R ( OSC is shown in Figure T Rosc connected to GND Rosc connected to Vccdr 0 100 200 300 400 500 Rosc (KOHM) Doc ID 11938 Rev 3 L6730 - L6730B ) connected between OSC pin (1) Ω ⋅ (2) Ω 600 700 800 900 1000 = 400 SW ...
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... CCDR at least 1 μF capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor. V CCDR CC/O/U pin (L6730B) and PGOOD pin (see ≈ the internal LDO works in dropout with an output resistance of about 1 Ω. If Vcc The maximum LDO output current is about 100 mA, and so the output voltage drop can be 100 mV ...
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... EAREF pin is captured by the device at the start-up when Vcc is about 4 V. 16/52 −> External reference CCDR −> 1.2 V CCDR REF −> 0.6 V CCDR REF Figure 7.). Finally it must be taken into account that the Doc ID 11938 Rev 3 L6730 - L6730B : with CC greater than 5 V the CC ...
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... L6730 - L6730B 5.5 Error amplifier Figure 7. Error amplifier reference V CCDR 5.6 Soft-start When both V and V CC pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp is generated charging the external capacitor C generator. The initial value for this current is 35 µA and charges the capacitor up to 0.5 V. ...
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... Start-up without pre-bias Figure 10. Start-up with pre-bias The L6730B can always sink current and so it can be used to supply the DDR memory termination BUS. If overcurrent is detected during the soft-start phase, the device provides constant current-protection. In case there is short soft-start time and/or small inductor value ...
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... V. After that the over current-protection triggers the HICCUP mode SS (L6730). With the L6730B there is the possibility to set the HICCUP mode or the constant current mode after the soft-start acting on the multifunction pin CC/O/U. With the L6730 the low-side MOSFET(s) management after soft-start phase depends on the S/O/U pin state (see related section) ...
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... PWM cycle. The predictive dead time control does not work when the high-side body diode is conducting because the phase node does not go 20/52 ), maintaining fast switching transitions. The DSON while the high-side driver is supplied by the BOOT pin. CCDR Figure 13.). Doc ID 11938 Rev 3 L6730 - L6730B Vout Vss Vcc I L ...
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... L6730 - L6730B negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates. Figure 13. Dead times 5.8 Monitoring and protection The output voltage is monitored by the FB pin not within ±10% (typ.) of the programmed value, the Power-Good (PGOOD) output is forced low. The PGOOD signal can ...
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... Device description turned on until V CC forced high (4.5 V typ over voltage is detected. Figure 14. PGOOD signal Figure 15. OVP not latched 22/52 is toggled (see Figure 16). In case of latched-mode OVP the OSC pin is Doc ID 11938 Rev 3 L6730 - L6730B FB PGOOD 2ms/Div. LGate FB OSC ...
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... L6730 - L6730B Figure 16. OVP latched There is an electrical network between the output terminal and the FB pin and therefore the voltage at this pin is not a perfect replica of the output voltage. If the converter can sink current, in the most of cases the low-side will be turned on before the output voltage exceeds the over-voltage threshold because the error amplifier will throw off balance in advance ...
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... Figure 17. OVP with sink enabled: the low-side MOSFET is turned-on in advance Figure 18. OVP with sink disabled: delay on the OVP operation The L6730B can always sink current and so the OVP will operate always in advance. The device realizes the over-current-protection (OCP) sensing the current both on the high-side ...
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... Figure 19. Constant current and hiccup mode during an OCP (L6730) Using the L6730B there is the possibility to set the constant-current-protection also after the soft-start. The following figures show the behaviour of the L6730B during an overcurrent event. ...
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... Device description Figure 20. Peak overcurrent-protection in constant-current-protection (L6730B) V OUT Figure 21. Peak OCP in case of heavy overcurrent (L6730B) V OUT OUT If the current is higher than the valley OCP threshold during the off-time, the high-side MOSFET(s) will not be turned ON. In this way the maximum current can be limited (Figure 22) ...
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... Multifunction pin (S/O/U L6730) (CC/O/U L6730B) With this pin it is possible: ● To enable disable the sink mode current capability (L6730) or the constant current protection (L6730B) at the end of the soft-start ● To enable or disable the latch-mode for the OVP ● To set the UVLO threshold for 5 V BUS and 12 V busses ...
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... EXT ) it is recommended to follow the below formula: SW ≤ ≤ EXT Doc ID 11938 Rev 3 L6730 - L6730B L6730/B OVP SINK CC Not latched Not latched Latched Latched Not latched Not latched Latched Latched ⋅ f ...
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... L6730 - L6730B The phase shift between master and slaves is approximately done 180°. Figure 24. Synchronization 5.12 Thermal shutdown When the junction temperature reaches 150°C ±10°C, the device enters in thermal shutdown. Both MOSFETs are turned OFF and the soft-start capacitor is rapidly discharged with an internal switch. The device does not restart until the junction temperature goes down to 120° ...
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... MOSFET cannot be effectively turned on and it will present a higher R some cases, the OCP can be also triggered. There are up to two conditions during which the bootstrap capacitor can be discharged: ● fan power supply failure, and ● no sink at zero current operation. 30/52 50ns Doc ID 11938 Rev 3 L6730 - L6730B . In DS(on) ...
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... With the L6730B, the current can be limited without shutting down the system because constant current protection is provided. In order to vary the motor speed, the output voltage of the converter must be varied. Both L6730 and L6730B have a dedicated EAREF pin (see Figure 4) which provides an external reference to the non-inverting input of the error- amplifier. In these applications the duty cycle depends on the motor’ ...
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... V -> 3.3 V can be observed that between two pulses trains the low-side is turned-on in order to keep the bootstrap cap charged. Figure 27 -> 3.3 V no-sink Minimum Bootstrap Voltage 32/52 Pulse train Doc ID 11938 Rev 3 L6730 - L6730B BOOT V PHASE ...
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... L6730 - L6730B 6 Application details 6.1 Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple current (ΔI ) between 20% and 30% of the maximum output current. The inductance value ...
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... Vout I ( ESR L ⋅ 8 Cout = ⋅ ⋅ − Irms Iout ⋅ ⋅ P ESR Iout Doc ID 11938 Rev 3 L6730 - L6730B ⋅ ESR (7) L (8) − max Vout ) (9) value can be set. The ESR and (10) ⋅ Fsw ) (11) /2 with D = 0.5. OUT 2 (12) ) OUT ...
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... L6730 - L6730B 6.4 Compensation network The loop is based on a voltage mode control the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output V pulse-width modulated (PWM) with an amplitude filtered by the output filter. The modulator transfer function is the small signal transfer ...
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... C Δ R Vosc 3 before the output filter resonance ω the output filter resonance ω the output capacitor ESR zero ω one half of the switching frequency; P2 Doc ID 11938 Rev 3 L6730 - L6730B 1 = (14) ESR ⋅ ESR Cout 1 = (16 ⋅ (18) ...
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... L6730 - L6730B 6.5 Two quadrant or one quadrant operation mode (L6730) After the soft-start phase the L6730 can work in source only (one quadrant operation mode sink/source (two quadrant operation mode), depending on the setting of the multifunction pin (see operation mode is related to the application. One quadrant operation mode permits to have ...
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... A. The switching frequency is set at 400 kHz (controller free- running F ) but it can be increased MHz positions dip-switch allows to select SW the UVLO threshold ( bus), the OVP intervention mode and the sink-mode current capability. Figure 32. Demonstration board picture Top Side 38/52 Doc ID 11938 Rev 3 L6730 - L6730B Bottom Side ...
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... L6730 - L6730B 7.2 PCB layout Figure 33. Top layer Figure 35. Signal ground layer Figure 34. Power ground layer Figure 36. Bottom layer Doc ID 11938 Rev 3 L6730 demonstration board 39/52 ...
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... Manufacturer Neohm 0Ω Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm 1K Neohm Doc ID 11938 Rev 3 L6730 - L6730B Package Supplier SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 ...
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... L6730 - L6730B Table 8. Demonstration board part list (continued) Reference Value R14 1K 1% 100mW R15 1K 1% 100mW R16 4K7 1% 100mW R17 N.C. R18 2.2Ω R19 2.2Ω R20 10K 1% 100mW R21 N.C. R22 N.C. R23 C1 220nF C3-C7-C9-C15-C21 100nF C2 1nF. C4-C6 100uF 20V C8 4 ...
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... TDK NIPPON CHEMI-CON PANASONIC 42/52 Series Inductor value (µH) 744318180 CDEP134-2R7MC-H HPI_13 T640 SPM12550T-1R0M220 FDA1254 HCF1305-1R0 HC5-1R0 Series Capacitor value (µF) C4532X5R1E156M C3225X5R0J107M 25PS100MJ12 ECJ4YB0J107M Doc ID 11938 Rev 3 L6730 - L6730B Saturation current (A) 1.8 20 2 2.2 14 1.15 22 1.3 27 Rated voltage ( 100 6 ...
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... L6730 - L6730B 8 I/O Description Figure 38. Demonstration board Table 11. I/O functions Symbol Input (Vin-Gin) Output (V -G OUT OUT V -GND CCDR TP1 The input voltage can range from 1.8V to 14V. If the input voltage is between 4.5V and 14V it can supply also the device (through the V case the pin 1 and 2 of the jumper G1 must be connected together ...
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... Not latched Yes Latched Not Latched Yes Not latched Not Not latched Yes Latched Not Latched Yes Doc ID 11938 Rev 3 L6730 - L6730B Function Table 4: Pin connection). Chapter 5.10 on page Chapter 5.11 on Vsou/V DIP switch CCDR 0 S7 0.2 S1-S7 0.3 S2-S7 0.4 S3-S7 0 ...
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... L6730 - L6730B 9 Efficiency The following figures show the demo board efficiency versus load current for different values of input voltage and switching frequency: Figure 39. Demonstration board efficiency 400 kHz 95.00% 90.00% 85.00% 80.00% 75.00% Figure 40. Demonstration board efficiency 645 kHz 95.00% 90.00% 85 ...
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... Figure 41. Demonstration board efficiency 1 MHz 95.00% 90.00% 85.00% 80.00% 75.00% 70.00% 65.00% 60.00% Figure 42. Efficiency with 2xSTS12NH3LL+2XSTSJ100NH3LL 0.96 0.95 0.94 0.93 0.92 0.91 0.9 0.89 0.88 0.87 3 46/52 Fsw=1MHz Iout (A) 12V-->3. OUTPUT CURRENT (A) Doc ID 11938 Rev 3 L6730 - L6730B 3. 12V 400KHz 700KHz 1MHz ...
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... L6730 - L6730B 10 POL demonstration board 10.1 Description A compact demonstration board has been designed to manage currents in the range of 10 Figure 39 shows the schematic and capacitors (MLCCs) have been used on the input and the output in order to reduce the overall size. Figure 43. Pol demonstration board schematic Table 13 ...
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... Kemet TDK MLC C4532X5R1E156M PANASONIC MLC P/N ECJ4YBOJ107M Panasonic 12V-->3.3V@400KHz 3 5 OUTPUT CURRENT (A) Doc ID 11938 Rev 3 L6730 - L6730B Package Supplier SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 IFARCAD SMD 0603 ...
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... L6730 - L6730B 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK trademark. Table 14. HTSSOP20 mechanical data Dim ( (2) E1 (3) E2 ...
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... Package mechanical data Figure 45. Package dimensions 50/52 Doc ID 11938 Rev 3 L6730 - L6730B ...
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... L6730 - L6730B 12 Revision history Table 15. Document revision history Date 21-Dec-2005 29-May-2006 07-Dec-2009 Revision 1 Initial release 2 New template, thermal data updated 3 Updated Table 4 on page 8 Doc ID 11938 Rev 3 Revision history Changes and added Section 1.2 on page 6 51/52 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 52/52 Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 11938 Rev 3 L6730 - L6730B ...