ISL65426IRZAS2698 Intersil, ISL65426IRZAS2698 Datasheet

IC REG DUAL SYNC BUCK 6A 50-QFN

ISL65426IRZAS2698

Manufacturer Part Number
ISL65426IRZAS2698
Description
IC REG DUAL SYNC BUCK 6A 50-QFN
Manufacturer
Intersil
Type
Step-Down (Buck)r
Datasheet

Specifications of ISL65426IRZAS2698

Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
2
Voltage - Output
1 ~ 4 V
Current - Output
6A
Frequency - Switching
1MHz
Voltage - Input
3 ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
50-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
6A Dual Synchronous Buck Regulator
with Integrated MOSFETs
The ISL65426 is a high efficiency dual output monolithic
synchronous buck converter operating over an input
voltage range of 3V to 5.5V. This single chip power solution
provides two output voltages, which are selectable or
externally adjustable from 1V to 80% of the supply voltage
while delivering up to 6A of total output current. The two
PWMs are synchronized 180
RMS input current and ripple voltage.
The ISL65426 switches at a fixed frequency of 1MHz and
utilizes current-mode control with integrated compensation
to minimize the size and number of external components
and provide excellent transient response. The internal
synchronous power switches are optimized for good
thermal performance and high efficiency.
A unique power block architecture allows partitioning of six
1A blocks to support one of four configuration options. One
master power block is associated with each synchronous
converter channel. Four floating slave power blocks allow
the user to assign them to either channel. Proper external
configuration of the power blocks is verified internally prior
to soft-start initialization.
Independent enable inputs allow for synchronization or
sequencing soft-start intervals of the two converter
channels. A third enable input allows additional sequencing
for multi-input bias supply designs. Individual power-good
indicators (PG1, PG2) signal when output voltage is within
the regulation window.
The ISL65426 integrates protection for both synchronous
buck regulator channels. The fault conditions include
overcurrent, undervoltage, and IC thermal monitor.
High integration contained in a thin Quad Flat No-lead
(QFN) package makes the ISL65426 an ideal choice to
power many of today’s small form factor applications. A
single chip solution for large scale digital ICs, like field
programmable gate arrays (FPGA), requiring separate core
and I/O voltages.
®
°
1
out-of-phase, reducing the
Data Sheet
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• High Efficiency: Up to 95%
• Fixed Frequency: 1MHz
• Operates From 3V to 5.5V Supply
• ±1% Reference
• Flexible Output Voltage Options
• User-Partitioned Power Blocks
• Ultra-Compact DC/DC Converter Design
• PWMs Synchronized 180
• Independent Enable Inputs and System Enable
• Stable All Ceramic Solutions
• Excellent Dynamic Response
• Independent Output Digital Soft-Start
• Power-Good Output Voltage Monitor
• Thermal-Overload Protection
• Overcurrent and Undervoltage Protection
• Pb-Free (RoHS Compliant)
Applications
• FPGA, CPLD, DSP, and CPU Core and I/O Voltages
• Low-Voltage, High-Density Distributed Power Systems
• Point-of-Load Regulation
• Distributed Power Systems
• Set-Top Boxes
Ordering Information
ISL65426HRZ* ISL65426 HRZ -10 to +100 50 Ld 5x10 QFN L50.5x10
ISL65426IRZA* ISL65426 IRZ
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach materials
and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
- Programmable 2-Bit VID Input
- Adjustable Output From 1V to 4.0V
- Xilinx Spartan III
- Altera Stratix
- Actel Fusion
NUMBER
Virtex 4
(Note)
PART
March 25, 2008
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
TM
Copyright © Intersil Americas Inc. 2006-2008. All Rights Reserved
TM
MARKING
TM
PART
,
,
LatticeSC
Stratix II
TM
, Virtex II
°
Out-of-Phase
TM
-40 to +85 50 Ld 5x10 QFN L50.5x10
TM
RANGE
TEMP.
,
(°C)
TM
, LatticeEC
Cyclone
,
Virtex II Pro
ISL65426
TM
PACKAGE
(Pb-free)
,
TM
Cyclone II
FN6340.3
TM
,
TM
DWG. #
PKG.

Related parts for ISL65426IRZAS2698

ISL65426IRZAS2698 Summary of contents

Page 1

... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006-2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL65426 FN6340 ...

Page 2

Pinout 2 ISL65426 ISL65426 (50 LD QFN) TOP VIEW PGND 1 42 PGND 2 41 PGND 3 40 PGND LX1 38 LX1 PVIN1 36 PVIN2 8 ...

Page 3

Typical Application Schematics 3. 1. FIGURE 1. TYPICAL APPLICATION FOR 3A:3A CONFIGURATION 3 ISL65426 SINGLE INPUT SUPPLY 3.3V 3.3V PVIN1 PVIN2 PVIN3 LX1 LX2 ISL65426 LX3 FB1 3.3V PVIN6 3.3V PVIN5 C4 PVIN4 LX6 L2 2.5V ...

Page 4

Typical Application Schematics 5. 1. FIGURE 2. TYPICAL APPLICATION FOR 4A:2A CONFIGURATION 4 ISL65426 (Continued) DUAL INPUT SUPPLY 3.3V 5.0V PVIN1 PVIN2 PVIN3 PVIN4 ISL65426 LX1 LX2 LX3 LX4 FB1 3.3V PVIN6 3.3V PVIN5 C4 LX6 ...

Page 5

Typical Application Schematics 5. 2.5V 5A FIGURE 3. TYPICAL APPLICATION FOR 5A:1A CONFIGURATION 5 ISL65426 (Continued) 5.0V 5.0V PVIN1 PVIN2 PVIN3 PVIN4 PVIN6 ISL65426 LX1 LX2 LX3 LX4 LX6 FB1 5.0V PVIN5 5. LX5 ...

Page 6

Functional Block Diagram SOFT-START FB1 V1SET1 OUTPUT VOLTAGE V1SET2 CONFIG PGOOD1 PWM REFERENCE 0.60V SOFT-START FB2 V2SET1 OUTPUT VOLTAGE CONFIG V2SET2 6 ISL65426 EN2 EN VCC GND POWER-ON RESET (POR) SLOPE COMPENSATION PWM EA GM CONTROL LOGIC COMPENSATION UV POWER-GOOD ...

Page 7

... Ambient Temperature Range (ISL65426HRZ .-10°C to +100°C Ambient Temperature Range (ISL65426IRZA .-40°C to +85°C Operating Junction Temperature Range . . . . . . . . .-10°C to +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = -40°C to +85°C for ISL65426IRZA. (Note 5) A TEST CONDITIONS EN1 = EN2 = EN = VCC = 5V, I ...

Page 8

Electrical Specifications Recommended operating conditions, unless otherwise noted. VCC = PVIN = 5.0V -10°C to +100°C for ISL65426HRZ and T A PARAMETER Upper Device r DS(ON) Lower Device r DS(ON) Efficiency POWER-ON RESET AND ENABLE PINS VCC POR ...

Page 9

Typical Performance Curves 100 3.3V 5. 0.1 1.0 2.0 OUTPUT LOAD (A) FIGURE 1.2V EFFICIENCY vs LOAD OUT1 100 5. ...

Page 10

Typical Performance Curves 1.235 1.225 1.215 5.5V IN 1.205 1.195 1.185 2.5V IN 1.175 1.165 0.1 1.0 2.0 OUTPUT LOAD (A) FIGURE 10 1.2V REGULATION vs LOAD OUT1 1.545 1.535 1.525 5.5V 1.515 1.505 1.495 1.485 2.5V 1.475 ...

Page 11

Typical Performance Curves 1.845 1.825 1.805 1.785 5.5V IN 1.765 1.745 0.1 0.5 1.0 OUTPUT LOAD (A) FIGURE 16 1.8V REGULATION vs LOAD OUT2 2.565 2.545 2.525 2.505 2.485 2.465 2.445 2.425 0.1 0.5 1.0 OUTPUT LOAD (A) ...

Page 12

Typical Performance Curves EN1 5V/DIV PG1 5V/DIV FIGURE 22. START- 1.2V (NO LOAD) OUT1 EN1 5V/DIV PG1 5V/DIV FIGURE 24. START- 1.2V (FULL LOAD) OUT1 EN2 5V/DIV PG2 5V/DIV FIGURE 26. START- 3.3V (NO ...

Page 13

Typical Performance Curves EN2 5V/DIV PG2 5V/DIV FIGURE 28. START- 3.3V (FULL-LOAD) OUT2 V RIPPLE 20mV/DIV OUT1 I 500mA/DIV OUT1 V RIPPLE 50mV/DIV OUT2 FIGURE 30 1.2V LOAD TRANSIENT OUT1 LX1 5V/DIV V 500mV/DIV OUT1 IL1 ...

Page 14

Typical Performance Curves FIGURE 34 PGND 1 PGND 2 PGND 3 PGND 4 5 LX1 6 LX1 7 PVIN1 PGND PVIN2 8 LX2 9 10 PGND 11 PGND 12 LX3 PVIN3 13 ...

Page 15

EN System enable for voltage monitoring with programmable hysteresis. This pin has a POR rising threshold of 0.6V. This enable is intended for applications where two or more input power supplies are used and bias rise time is an issue. ...

Page 16

Table 2. When each pin is pulled to GND by an internal 10µA pull-down, this default condition programs the output voltage to the lowest level. The pull-down prevents situations where a pin could be left floating for example (cold ...

Page 17

Equation 2. R VCC2 and R is the resistor from EN to GND. 2 0.6V ⋅ ------------ + 10μA + 0.6V ENABLE Once the voltage at the EN pin ...

Page 18

... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides a complete reference design that includes schematics, a bill of materials and example board layout. Output Filter Design ...

Page 19

Equation 4. di ΔV ≈ × [ × ΔI ] ESL ---- - ESR + dt The filter capacitors selected must have sufficiently low ESL and ESR so ...

Page 20

The following multi-layer printed circuitry board layout strategies minimize the impact of board parasitics on converter performance and optimize the heat-dissipating capabilities of the printed circuit board. This section highlights some important practices which should not be overlooked during the ...

Page 21

Sensitive signals should be routed on different layers or some distance away from the PHASE plane on the same layer. Crosstalk due to switching noise is reduced into these lines by isolating the routing path away from the PHASE plane. ...

Page 22

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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