MAX15046BAEE+ Maxim Integrated Products, MAX15046BAEE+ Datasheet - Page 16

IC CTLR SYNC BUCK 40V 16-QSOP

MAX15046BAEE+

Manufacturer Part Number
MAX15046BAEE+
Description
IC CTLR SYNC BUCK 40V 16-QSOP
Manufacturer
Maxim Integrated Products
Type
Step-Down (Buck)r
Datasheet

Specifications of MAX15046BAEE+

Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.6 ~ 34 V
Current - Output
3A
Frequency - Switching
100kHz ~ 1MHz
Voltage - Input
4.5 ~ 40 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-QSOP
Power - Output
771.5mW
Output Voltage
0.6 V to 34 V
Output Current
25 A
Output Power
1818.2 mW
Input Voltage
4.5 V to 40 V
Switching Frequency
100 KHz to 1000 KHz
Mounting Style
SMD/SMT
Duty Cycle (max)
87.5 %
Primary Input Voltage
40V
No. Of Outputs
1
No. Of Pins
16
Operating Temperature Range
-40°C To +125°C
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
40V, High-Performance, Synchronous
Buck Controller
The MAX15046 provides an internal transconductance
amplifier with the inverting input and the output available
for external frequency compensation. The flexibility of
external compensation offers wide selection of output
filtering components, especially the output capacitor.
Use high-ESR aluminum electrolytic capacitors for cost-
sensitive applications. Use low-ESR tantalum or ceramic
capacitors at the output for size-sensitive applications.
The high switching frequency of the MAX15046 allows
the use of ceramic capacitors at the output. Choose all
passive power components to meet the output ripple,
component size, and component cost requirements.
Choose the compensation components for the error
amplifier to achieve the desired closed-loop bandwidth
and phase margin.
To choose the appropriate compensation network type,
the power-supply poles and zeros, the zero-crossover
frequency, and the type of the output capacitor must be
determined first.
In a buck converter, the LC filter in the output stage intro-
duces a pair of complex poles at the following frequency:
The output capacitor introduces a zero at:
where ESR is the equivalent series resistance of the
output capacitor.
The loop-gain crossover frequency (f
gain equals 1 (0dB) should be set below 1/10th of the
switching frequency:
Choosing a lower crossover frequency reduces the
effects of noise pickup into the feedback loop, such as
jittery duty cycle.
To maintain a stable system, two stability criteria must
be met:
1) The phase shift at the crossover frequency, f
16
be less than 180N. In other words, the phase margin
of the loop must be greater than zero.
_____________________________________________________________________________________
f
PO
f
ZO
=
=
2
π ×
2
f
π ×
O
L
ESR C
Compensation Design
OUT
f
SW
10
1
1
×
×
C
OUT
OUT
O
), where the loop
O
, must
2) The gain at the frequency where the phase shift is
Maintain a phase margin of around 60N to achieve a robust
loop stability and well-behaved transient response.
When using an electrolytic or large-ESR tantalum output
capacitor, the capacitor ESR zero f
between the LC poles and the crossover frequency f
(f
Integral) compensation network.
When using a ceramic or low-ESR tantalum output
capacitor, the capacitor ESR zero typically occurs above
the desired crossover frequency f
f
Derivative) compensation network.
If f
the capacitor ESR zero almost cancels the phase loss of
one of the complex poles of the LC filter around the cross-
over frequency. Use a Type II compensation network with
a midband zero and a high-frequency pole to stabilize
the loop. In Figure 3, R
zero (f
work provide a high-frequency pole (f
the effects of the output high-frequency ripple.
Use the following steps to calculate the component
values for Type II compensation network as shown in
Figure 3:
1) Calculate the gain of the modulator (GAIN
where V
is the amplitude of the ramp in the pulse-width modula-
tor, V
see the Electrical Characteristics table), and V
desired output voltage.
The gain of the error amplifier (GAIN
frequencies is:
where g
ZO
PO
ZO
-180N (gain margin) must be less than 1.
comprised of the regulator’s pulse-width modulator,
LC filter, feedback divider, and associated circuitry
at crossover frequency:
. Choose the Type III (PID- Proportional, Integral, and
GAIN
< f
FB
is lower than f
Z1
M
ZO
IN
is the FB input voltage set point (0.6V typically,
). R
MOD
is the transconductance of the error amplifier.
is the input voltage of the regulator, V
< f
F
and C
O
=
Type II Compensation Network
). Choose the Type II (PI-Proportional,
V
GAIN
O
RAMP
V
CF
IN
and close to f
in the Type II compensation net-
EA
F
×
and C
= g
(
2
π ×
M
F
f
x R
O
ESR
O
introduce a midband
PO
×
, that is f
F
ZO
P1
L
, the phase lead of
OUT
), which mitigates
EA
typically occurs
) in midband
)
(Figure 3)
×
PO
V
OUT
V
OUT
FB
< f
MOD
RAMP
is the
O
O
<
),

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