MAX15046BAEE+ Maxim Integrated Products, MAX15046BAEE+ Datasheet - Page 17

IC CTLR SYNC BUCK 40V 16-QSOP

MAX15046BAEE+

Manufacturer Part Number
MAX15046BAEE+
Description
IC CTLR SYNC BUCK 40V 16-QSOP
Manufacturer
Maxim Integrated Products
Type
Step-Down (Buck)r
Datasheet

Specifications of MAX15046BAEE+

Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.6 ~ 34 V
Current - Output
3A
Frequency - Switching
100kHz ~ 1MHz
Voltage - Input
4.5 ~ 40 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-QSOP
Power - Output
771.5mW
Output Voltage
0.6 V to 34 V
Output Current
25 A
Output Power
1818.2 mW
Input Voltage
4.5 V to 40 V
Switching Frequency
100 KHz to 1000 KHz
Mounting Style
SMD/SMT
Duty Cycle (max)
87.5 %
Primary Input Voltage
40V
No. Of Outputs
1
No. Of Pins
16
Operating Temperature Range
-40°C To +125°C
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The total loop gain, which is the product of the modulator
gain and the error-amplifier gain at f
1) GAIN
2) Set a midband zero (f
Solving for C
3) Place a high-frequency pole at f
So :
Solving for R :
Figure 3. Type II Compensation Network
R
of the LC poles):
attenuate the ripple at the switching frequency f
and calculate C
V
F
V
OSC
IN
=
V
MOD
V
OSC
×
OUT
(2
R
R
F
f
2
1
F
Z1
π ×
V
×
:
× π ×
C
FB
C
GAIN
=
(
2
F
f
CF
O
ESR
______________________________________________________________________________________
2
V
×
REF
=
π ×
CF
×
V
2
=
IN
EA
L
f
O
π ×
R
using the following equation:
OUT
π ×
×
1
F
×
=
R
g
Z1
L
×
40V, High-Performance, Synchronous
R
1
M
F
)
OUT
C
) at 0.75 x f
F
g
M
×
×
×
F
×
1
V
f
ESR
1
PO
f
V
=
OUT
)
SW
FB
×
0.75 f
C
R
×
F
V
F
-
OUT
0.75
C
×
O
1
P1
×
F
, is:
g
PO
M
PO
= 0.5 x f
×
(to cancel one
R
COMP
F
C
CF
=
1
SW
SW
(to
)
When using a low-ESR tantalum or ceramic type, the
ESR-induced zero frequency is usually above the tar-
geted zero crossover frequency (f
pensation. Type III compensation provides two zeros
and three poles at the following frequencies:
Two midband zeros (f
plex poles introduced by the LC filter:
f
nulling DC output-voltage errors:
Depending on the location of the ESR zero (f
to cancel f
high-frequency output ripple:
f
Place the zeros and poles such that the phase margin
peaks around f
Ensure that R
R
phase shift is introduced to the response making the
loop unstable.
Use the following compensation procedures:
1) With R
P1
P3
1
, R
f
attenuates the high-frequency output ripple.
PO
introduces a pole at zero frequency (integrator) for
2
:
, and R
F
ZO
>> 10kI, place the first zero (f
, or to provide additional attenuation of the
f
F
I
Z1
f
O
P3
Type III Compensation Network
is greater than 1/g
>> 2/g
f
f
.
Z1
Z2
=
Buck Controller
=
f
2
P2
=
=
2
π ×
2
π ×
Z1
2
π ×
=
π ×
M
R
and f
2
f
R
1
F
P1
R
π ×
and the parallel resistance of
C
F
1
×
F
I
×
= 0
C
×
×
R
1
1
1
Z2
C
C
(R
F
C
I
×
F
F
F
) cancel the pair of com-
1
=
C
×
+
+
0.8 f
O
I
C
M
C
R )
). Use Type III com-
I
. Otherwise, a 180N
CF
CF
×
(See Figure 4)
PO
ZO
Z1
) at 0.8 x
), use f
17
P2

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