IDT89HPES12N3A1ZCBCG8

Manufacturer Part NumberIDT89HPES12N3A1ZCBCG8
DescriptionIC PCI SW 12LANE 3PORT 324-BGA
ManufacturerIDT, Integrated Device Technology Inc
IDT89HPES12N3A1ZCBCG8 datasheets

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Specifications of IDT89HPES12N3A1ZCBCG8

Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names89HPES12N3A1ZCBCG8
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®
Device Overview
The 89HPES12N3A is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES12N3A is a 12-lane, 3-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
Features
◆
High Performance PCI Express Switch
– Twelve 2.5Gbps PCI Express lanes
– Three switch ports
– Upstream port configurable up to x4
– Downstream ports configurable up to x4
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Block Diagram
Frame Buffer
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Phy
Phy
Phy
Logical
Logical
Logical
Logical
Layer
Layer
Layer
Layer
SerDes
SerDes
SerDes
SerDes
One x4 Upstream Port and Two x4 Downstream Ports
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
© 2010 Integrated Device Technology, Inc.
12-lane 3-Port
PCI Express® Switch
◆
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆
Legacy Support
– PCI compatible INTx emulation
– Bus locking
Highly Integrated Solution
◆
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates twelve 2.5 Gbps embedded SerDes with 8B/10B
◆
Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
3-Port Switch Core
Port
Route Table
Arbitration
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Phy
Phy
Phy
Logical
Logical
Logical
Logical
Layer
Layer
Layer
Layer
SerDes
SerDes
SerDes
SerDes
12 PCI Express Lanes
Figure 1 Internal Block Diagram
1 of 31
89HPES12N3A
Data Sheet
queueing
encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
server motherboards
Scheduler
Scheduler
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Phy
Phy
Phy
Logical
Logical
Logical
Logical
Layer
Layer
Layer
Layer
SerDes
SerDes
SerDes
SerDes
April 9, 2010
DSC 6922

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IDT89HPES12N3A1ZCBCG8 Summary of contents

  • Page 1

    Device Overview The 89HPES12N3A is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES12N3A is a 12-lane, 3-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high performance ...

  • Page 2

    IDT 89HPES12N3A Data Sheet ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCI-PM 1.1) • Supports device power management states: D0 cold – Unused ...

  • Page 3

    IDT 89HPES12N3A Data Sheet Processor SMBus PES12N3A Master SSMBCLK SSMBDAT MSMBCLK MSMBDAT (a) Unified Configuration and Management Bus Hot-Plug Interface The PES12N3A supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, ...

  • Page 4

    IDT 89HPES12N3A Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12N3A. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using ...

  • Page 5

    IDT 89HPES12N3A Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] Signal CCLKDS CCLKUS MSMBSMODE Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate ...

  • Page 6

    IDT 89HPES12N3A Data Sheet Signal PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE Type Name/Description I Fundamental Reset. Assertion of this signal resets all logic inside the PES12N3A and ...

  • Page 7

    IDT 89HPES12N3A Data Sheet Signal V APE Type Name/Description I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. I PCI Express Termination Power. I Ground. Table 7 ...

  • Page 8

    IDT 89HPES12N3A Data Sheet Pin Characteristics Note: Some input pads of the PES12N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if ...

  • Page 9

    IDT 89HPES12N3A Data Sheet Function JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 1. Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. 2. Schmitt Trigger Input (STI). Pin Name Type Buffer I LVTTL ...

  • Page 10

    IDT 89HPES12N3A Data Sheet Logic Diagram — PES12N3A Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 4 Master SMBus Interface SSMBADDR[5,3:1] Slave SMBus Interface System Functions ...

  • Page 11

    IDT 89HPES12N3A Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of input ...

  • Page 12

    IDT 89HPES12N3A Data Sheet Parameter T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ENTER TIME T Lane to lane input skew RX-SKEW 1. Minimum, Typical, and ...

  • Page 13

    IDT 89HPES12N3A Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a ...

  • Page 14

    IDT 89HPES12N3A Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power ...

  • Page 15

    IDT 89HPES12N3A Data Sheet Core Supply Number of active Lanes per Port Typ 1.0V 4/4/4 mA 723 Watts 0.72 4/1/1 mA 618 Watts 0.62 Thermal Considerations This section describes thermal considerations for the PES12N3A (19mm is relevant to the thermal ...

  • Page 16

    IDT 89HPES12N3A Data Sheet Thermal Usage Examples The junction-to-ambient thermal resistance is a measure of a device’s ability to dissipate heat from the die to its surroundings in the absence of a heat sink. The general formula to determine θ ...

  • Page 17

    IDT 89HPES12N3A Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V ...

  • Page 18

    IDT 89HPES12N3A Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN ...

  • Page 19

    IDT 89HPES12N3A Data Sheet Package Pinout — 324-BGA Signal Pinout for PES12N3A The following table lists the pin numbers and signal names for the PES12N3A device. Pin Function Alt Pin A1 V E10 E11 SS A3 PE0RP03 ...

  • Page 20

    IDT 89HPES12N3A Data Sheet Pin Function Alt Pin B17 V CORE G8 DD B18 V CORE PE2RP00 G10 C2 PE2RN00 G11 C3 V G12 CORE G13 G14 ...

  • Page 21

    IDT 89HPES12N3A Data Sheet Pin Function Alt Pin D18 V CORE PE2TN00 J10 E2 PE2TP00 J11 E3 V CORE J12 J13 CORE J14 J15 J16 ...

  • Page 22

    IDT 89HPES12N3A Data Sheet Power Pins V Core V Core A10 F10 A12 F18 A14 G12 A15 B17 H10 B18 H12 C4 H18 C13 J6 C16 J9 ...

  • Page 23

    IDT 89HPES12N3A Data Sheet Ground Pins A17 A18 B10 B12 B14 B15 C11 D11 D13 D15 G11 D16 G13 D17 ...

  • Page 24

    IDT 89HPES12N3A Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 PE0RP01 ...

  • Page 25

    IDT 89HPES12N3A Data Sheet Signal Name PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 PE4RP02 PE4RP03 PE4TN00 PE4TN01 PE4TN02 ...

  • Page 26

    IDT 89HPES12N3A Data Sheet Signal Name PE4TP01 PE4TP02 PE4TP03 PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 CORE APE ...

  • Page 27

    IDT 89HPES12N3A Data Sheet PES12N3A Pinout — Top View Core (Power I/O (Power ...

  • Page 28

    IDT 89HPES12N3A Data Sheet PES12N3A Package Drawing — 324-Pin BC324/BCG324 April 9, 2010 ...

  • Page 29

    IDT 89HPES12N3A Data Sheet PES12N3A Package Drawing — Page Two April 9, 2010 ...

  • Page 30

    IDT 89HPES12N3A Data Sheet Revision History February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Added ZG device revision to Ordering Information. November 14, 2007: Added new parameter, Termination Resistor, ...

  • Page 31

    IDT 89HPES12N3A Data Sheet Ordering Information A AAA NN Product Operating Device Family Family Voltage Valid Combinations 89HPES12N3AZCBC 324-pin BC324 package, Commercial Temp. 89HPES12N3AZGBC 324-pin BC324 package, Commercial Temp. 89HPES12N3A1ZCBC 324-pin BC324 package, Commercial Temp. 89HPES12N3AZCBCG 324-pin Green BC324 package, ...

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