IDT89HPES12NT3ZBBCG8

Manufacturer Part NumberIDT89HPES12NT3ZBBCG8
DescriptionIC PCI SW 12LANE 3PORT 324-BGA
ManufacturerIDT, Integrated Device Technology Inc
IDT89HPES12NT3ZBBCG8 datasheets

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Specifications of IDT89HPES12NT3ZBBCG8

Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names89HPES12NT3ZBBCG8
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®
Device Overview
The 89HPES12NT3 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions offering the next-generation I/O inter-
connect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip
that performs PCI Express Base switching with a feature set optimized
for high performance applications such as servers, storage, and commu-
nications/networking. It provides high-performance I/O connectivity and
switching functions between a PCIe® upstream port, a transparent
downstream port, and a non-transparent downstream port.
With non-transparent bridging (NTB) functionality, the PES12NT3
can be used standalone or as a chipset with IDT PCIe System Intercon-
nect Switches in multi-host and intelligent I/O applications such as
communications, storage, and blade servers where inter-domain
communication is required.
Features
◆
High Performance PCI Express Switch
– Twelve PCI Express lanes (2.5Gbps), three switch ports
– Delivers 48 Gbps (6 GBps) of aggregate switching capacity
– Low latency cut-through switch architecture
– Support for Max Payload size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– PCI Express Base specification Revision 1.0a compliant
Block Diagram
Frame Buffer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Logical
Logical
Logical
...
Layer
Layer
SerDes
SerDes
SerDes
x4 Upstream Port and Two x4 Downstream Ports
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
© 2009 Integrated Device Technology, Inc.
12-lane 3-Port Non-Transparent
PCI Express® Switch
◆
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin
– Supports automatic per port link width negotiation (x4, x2, or
– Static lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy soft-
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
◆
Non-Transparent Port
– Crosslink support on NTB port
– Four mapping windows supported
– Interprocessor communication
– Allows up to sixteen masters to communicate through the non-
– No limit on the number of supported outstanding transactions
– Completely symmetric non-transparent bridge operation
– Supports direct connection to a transparent or non-transparent
3-Port Switch Core
Port
Route Table
Arbitration
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Phy
Logical
Logical
Logical
...
Layer
Layer
Layer
Layer
SerDes
SerDes
SerDes
12 PCI Express Lanes
Figure 1 Internal Block Diagram
1 of 29
89HPES12NT3
Data Sheet
x1)
ware
• Each may be configured as a 32-bit memory or I/O window
• May be paired to form a 64-bit memory window
• Thirty-two inbound and outbound doorbells
• Four inbound and outbound message registers
• Two shared scratchpad registers
transparent port
through the non-transparent bridge
allows similar/same configuration software to be run
port of another switch
Scheduler
Transaction Layer
Non-
Transparent
Bridge
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical
Logical
Logical
...
Layer
Layer
Layer
SerDes
SerDes
SerDes
Inc.
February 19, 2009
DSC 6929

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IDT89HPES12NT3ZBBCG8 Summary of contents

  • Page 1

    Device Overview The 89HPES12NT3 is a member of the IDT PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O inter- connect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip that performs PCI Express Base switching with ...

  • Page 2

    IDT 89HPES12NT3 Data Sheet ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twelve 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) ◆ Reliability, ...

  • Page 3

    IDT 89HPES12NT3 Data Sheet PCIe System Interconnect Switch To Server CPU CPU PES12NT3 PES12NT3 PCIe System Interconnect Switch Embedded Embedded CPU CPU FC SATA / SAS Figure 2 PCIe System Interconnect Architecture Block Diagram Controller 1 CPU Cache Maint. & ...

  • Page 4

    IDT 89HPES12NT3 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12NT3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using ...

  • Page 5

    IDT 89HPES12NT3 Data Sheet Signal SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] Type Name/Description I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. I/O Slave SMBus Clock. ...

  • Page 6

    IDT 89HPES12NT3 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PENTBRSTN PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI Type Name/Description I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream ...

  • Page 7

    IDT 89HPES12NT3 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description O JTAG Data Output. This is the serial data shifted out from ...

  • Page 8

    IDT 89HPES12NT3 Data Sheet Pin Characteristics Note: Some input pads of the PES12NT3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if ...

  • Page 9

    IDT 89HPES12NT3 Data Sheet Function System Pins JTAG Pin Name Type Buffer CCLKDS I LVTTL CCLKUS I MSMBSMODE I PENTBRSTN I PERSTN I RSTHALT I SWMODE[3:0] I JTAG_TCK I LVTTL JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_TRST_N I Table 7 ...

  • Page 10

    IDT 89HPES12NT3 Data Sheet Logic Diagram — PES12NT3 Reference Clock PCI Express Switch SerDes Input Port A PCI Express Switch SerDes Input Port B PCI Express Switch SerDes Input Port C Master SMBus Interface SSMBADDR[5,3:1] Slave SMBus Interface System Pins ...

  • Page 11

    IDT 89HPES12NT3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of input ...

  • Page 12

    IDT 89HPES12NT3 Data Sheet Parameter T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ENTER TIME T Lane to lane input skew RX-SKEW 1. Minimum, Typical, and ...

  • Page 13

    IDT 89HPES12NT3 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express ...

  • Page 14

    IDT 89HPES12NT3 Data Sheet Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES12NT3, the power-up sequence must be as follows I/O ...

  • Page 15

    IDT 89HPES12NT3 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V ...

  • Page 16

    IDT 89HPES12NT3 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN ...

  • Page 17

    IDT 89HPES12NT3 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES12NT3 The following table lists the pin numbers and signal names for the PES12NT3 device. Pin Function Alt Pin A1 V E10 E11 SS A3 PEARP03 ...

  • Page 18

    IDT 89HPES12NT3 Data Sheet Pin Function Alt Pin B17 V CORE G8 DD B18 V CORE PEBRP00 G10 C2 PEBRN00 G11 C3 V G12 CORE G13 G14 ...

  • Page 19

    IDT 89HPES12NT3 Data Sheet Pin Function Alt Pin D18 V CORE PEBTN00 J10 E2 PEBTP00 J11 E3 V CORE J12 J13 CORE J14 J15 J16 ...

  • Page 20

    IDT 89HPES12NT3 Data Sheet Power Pins V Core V Core A10 F10 A12 F18 A14 G12 A15 B17 H10 B18 H12 C4 H18 C13 J6 C16 J9 ...

  • Page 21

    IDT 89HPES12NT3 Data Sheet Ground Pins A17 A18 B10 B12 B14 B15 C11 D11 D13 D15 D16 G16 D17 H2 ...

  • Page 22

    IDT 89HPES12NT3 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE PEALREV PEARN00 PEARN01 PEARN02 PEARN03 PEARP00 PEARP01 PEARP02 PEARP03 ...

  • Page 23

    IDT 89HPES12NT3 Data Sheet Signal Name PEATN03 PEATP00 PEATP01 PEATP02 PEATP03 PEBLREV PEBRN00 PEBRN01 PEBRN02 PEBRN03 PEBRP00 PEBRP01 PEBRP02 PEBRP03 PEBTN00 PEBTN01 PEBTN02 PEBTN03 PEBTP00 PEBTP01 PEBTP02 PEBTP03 PECLREV PECRN00 PECRN01 PECRN02 PECRN03 PECRP00 PECRP01 PECRP02 PECRP03 PECTN00 PECTN01 PECTN02 ...

  • Page 24

    IDT 89HPES12NT3 Data Sheet Signal Name PECTP01 PECTP02 PECTP03 PENTBRSTN PEREFCLKN0 PEREFCLKN1 PEREFCLKP0 PEREFCLKP1 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE ...

  • Page 25

    IDT 89HPES12NT3 Data Sheet PES12NT3 Pinout — Top View Core (Power I/O (Power ...

  • Page 26

    IDT 89HPES12NT3 Data Sheet PES12NT3 Package Drawing — 324-Pin BC324/BCG324 February 19, 2009 ...

  • Page 27

    IDT 89HPES12NT3 Data Sheet PES12NT3 Package Drawing — Page Two February 19, 2009 ...

  • Page 28

    IDT 89HPES12NT3 Data Sheet Revision History April 15, 2008: Initial publication of data sheet. January 5, 2009: On the Ordering Information page, changed silicon revision from ZA to ZB. February 19, 2009: Added industrial temperature to Table 13 and to ...

  • Page 29

    IDT 89HPES12NT3 Data Sheet Ordering Information A AAA NN Product Operating Device Family Family Voltage Valid Combinations 89HPES12NT3ZBBC 324-pin BC324 package, Commercial Temperature 89HPES12NT3ZBBCG 324-pin Green BC324 package, Commercial Temperature 89HPES12NT3ZBBCI 324-pin BC324 package, Industrial Temperature 89HPES12NT3ZBBCGI 324-pin Green BC324 ...

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