IDT89HPES12N3YCBC

Manufacturer Part NumberIDT89HPES12N3YCBC
DescriptionIC PCI SW 12LANE 3PORT 324-BGA
ManufacturerIDT, Integrated Device Technology Inc
IDT89HPES12N3YCBC datasheets

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Specifications of IDT89HPES12N3YCBC

Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names89HPES12N3YCBC
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Device Overview
The PES12N3, a 12 lane 3-port PCI Express® switch, is a member
of IDT’s PRECISE™ family of PCI Express switching solutions. The
PES12N3 is a peripheral chip that performs PCI Express Base switching
with a feature set optimized for high performance applications such as
servers and storage. It provides connectivity and switching functions
between a PCI Express upstream port and two downstream ports or
peer-to-peer switching between downstream ports.
Features
◆
High Performance PCI Express Switch
– Three x4 ports with 12 PCI lanes total
– Delivers 6 GBps (48 Gbps) aggregate switching capacity
– Low latency cut-through switch architecture
– Supports 128 to 256 byte maximum payload size
– Supports one virtual channel
– PCI Express Base specification Revision 1.0a compliant
◆
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin or weighted
round robin algorithms
– Supports automatic per port link with negotiation (x4, x2, or x1)
– Supports static lane reversal on all ports
– Supports polarity inversion
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
Block Diagram
Frame Buffer
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Phy
Phy
Phy
Logical
Logical
Logical
Logical
Layer
Layer
Layer
Layer
SerDes
SerDes
SerDes
SerDes
One x4 Upstream Port and Two x4 Downstream Ports
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
© 2006 Integrated Device Technology, Inc.
12 Lane 3-Port PCI Express® Switch
◆
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/
◆
– Internal end-to-end parity protection on all TLPs ensures data
– Supports ECRC passed through
– Supports PCI Express Native Hot-Plug
– Supports Hot-Swap
◆
– Supports PCI Express Power Management Interface Specifi-
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Speci-
◆
– Supports IEEE 1149.6 JTAG
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
3-Port Switch Core
Route Table
Arbitration
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Phy
Phy
Logical
Logical
Logical
Logical
Layer
Layer
Layer
SerDes
SerDes
SerDes
SerDes
12 PCI Express Lanes
1 of 2
Product Brief
Highly Integrated Solution
queueing
decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
integrity even in systems that do not implement end-to-end
CRC (ECRC)
• Compatible with Hot-Plug I/O expanders used on PC moth-
erboards
Power Management
cation, Revision 1.1 (PCI-PM)
fication, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
Port
Scheduler
Scheduler
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Phy
Phy
Phy
Logical
Logical
Logical
Layer
Layer
Layer
Layer
SerDes
SerDes
SerDes
89PES12N3
Phy
Logical
Layer
SerDes
February 15, 2006
DSC 6801

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IDT89HPES12N3YCBC Summary of contents

  • Page 1

    Device Overview The PES12N3 lane 3-port PCI Express® switch member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES12N3 is a peripheral chip that performs PCI Express Base switching with a feature set optimized ...

  • Page 2

    IDT ◆ Two SMBus Interfaces ◆ 8 General Purpose Input/Output pins ◆ Packaged in 19x19mm 324 ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect the PES12N3 provides the most efficient high-performance I/O connectivity device for ...

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