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IDT89HPES16T7ZHBX
IDT89HPES16T7ZHBX | |
|---|---|
| Manufacturer Part Number | IDT89HPES16T7ZHBX |
| Description | IC PCI SW 16LANE 7PORT 320-SBGA |
| Manufacturer | IDT, Integrated Device Technology Inc |
| IDT89HPES16T7ZHBX datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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- If you still have any questions - please contact us
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Specifications of IDT89HPES16T7ZHBX | |||
|---|---|---|---|
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Other names | 89HPES16T7ZHBX |
PrevNext
IDT 89HPES16T7 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter
PEREFCLK
Refclk
Input reference clock frequency range
FREQ
2
Refclk
Duty cycle of input clock
DC
T
, T
Rise/Fall time of input clocks
R
F
V
Differential input voltage swing
SW
T
Input clock jitter (cycle-to-cycle)
jitter
R
Termination Resistor
T
1.
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
2.
ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
3.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
4.
AC coupling required.
AC Timing Characteristics
Parameter
PCIe Transmit
UI
Unit Interval
T
Minimum Tx Eye Width
TX-EYE
T
Maximum time between the jitter median and maximum
TX-EYE-MEDIAN-to-
deviation from the median
MAX-JITTER
T
, T
D+ / D- Tx output rise/fall time
TX-RISE
TX-FALL
T
Minimum time in idle
TX- IDLE-MIN
T
Maximum time to transition to a valid Idle after sending
TX-IDLE-SET-TO-
an Idle ordered set
IDLE
T
Maximum time to transition from valid idle to diff data
TX-IDLE-TO-DIFF-
DATA
T
Transmitter data skew between any 2 lanes
TX-SKEW
PCIe Receive
UI
Unit Interval
T
Minimum Receiver Eye Width (jitter tolerance)
RX-EYE (with jitter)
T
Max time between jitter median & max deviation
RX-EYE-MEDIUM TO
MAX JITTER
T
Unexpected Idle Enter Detect Threshold Integration Time
RX-IDLE-DET-DIFF-
ENTER TIME
T
Lane to lane input skew
RX-SKEW
Description
Min
4
Table 9 Input Clock Requirements
Description
Min
399.88
399.88
Table 10 PCIe AC Timing Characteristics
13 of 33
Typical
Max
1
100
125
40
50
60
0.2*RCUI
0.6
1.6
125
110
1
1
1
Typical
Max
400
400.12
0.7
.9
0.15
50
90
50
20
20
500
1300
400
400.12
0.4
0.3
10
20
Unit
MHz
%
3
RCUI
V
ps
Ohms
Units
ps
UI
UI
ps
UI
UI
UI
ps
ps
UI
UI
ms
ns
March 25, 2008
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