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IDT89HPES16T7ZHBX
IDT89HPES16T7ZHBX | |
|---|---|
| Manufacturer Part Number | IDT89HPES16T7ZHBX |
| Description | IC PCI SW 16LANE 7PORT 320-SBGA |
| Manufacturer | IDT, Integrated Device Technology Inc |
| IDT89HPES16T7ZHBX datasheets |
|
Availability: In stock
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Specifications of IDT89HPES16T7ZHBX | |||
|---|---|---|---|
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Other names | 89HPES16T7ZHBX |
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IDT 89HPES16T7 Data Sheet
SMBus Interface
The PES16T7 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES16T7, allowing
every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register
values of the PES16T7 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used
by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
As shown in Figure 4, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
4(a), the master and slave SMBuses are tied together and the PES16T7 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES16T7 registers supports SMBus arbitration. In some systems, this SMBus master
interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support
these systems, the PES16T7 may be configured to operate in a split configuration as shown in Figure 4(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES16T7 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the
serial EEPROM.
Processor
SMBus
PES16T7
Master
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
(a) Unified Configuration and Management Bus
Slave
Bit
SMBus
Address
1
SSMBADDR[1]
2
SSMBADDR[2]
3
SSMBADDR[3]
4
0
5
SSMBADDR[5]
6
1
7
1
Table 1 Master and Slave SMBus Address Assignment
Other
...
Serial
SMBus
EEPROM
Devices
(b) Split Configuration and Management Buses
Figure 4 SMBus Interface Configuration Examples
3 of 33
Master
SMBus
Address
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
1
0
1
Processor
Other
...
SMBus
SMBus
PES16T7
Master
Devices
SSMBCLK
SSMBDAT
MSMBCLK
Serial
EEPROM
MSMBDAT
March 25, 2008
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