IDT89HPES16T7ZHBX

Manufacturer Part NumberIDT89HPES16T7ZHBX
DescriptionIC PCI SW 16LANE 7PORT 320-SBGA
ManufacturerIDT, Integrated Device Technology Inc
IDT89HPES16T7ZHBX datasheets

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Specifications of IDT89HPES16T7ZHBX

Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names89HPES16T7ZHBX
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IDT 89HPES16T7 Data Sheet
Hot-Plug Interface
The PES16T7 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES16T7
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES16T7 generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES16T7. In response to an I/O expander interrupt, the PES16T7 generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES16T7 provides 12 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES16T7. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PE0RP[3:0]
PE0RN[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1RN[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE2RP[0]
PE2RN[0]
PE2TP[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TP[0]
PE3TN[0]
PE4RP[0]
PE4RN[0]
PE4TP[0]
PE4TN[0]
PE5RP[0]
PE5RN[0]
PE5TP[0]
PE5TN[0]
PE6RP[3:0]
PE6RN[3:0]
Type
Name/Description
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
I
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1.
O
PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1.
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 4.
I
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pair for port 5.
O
PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 5.
I
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pair for port 6.
Table 2 PCI Express Interface Pins (Part 1 of 2)
4 of 33
March 25, 2008

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