IDT89HPES16T7ZHBX

Manufacturer Part NumberIDT89HPES16T7ZHBX
DescriptionIC PCI SW 16LANE 7PORT 320-SBGA
ManufacturerIDT, Integrated Device Technology Inc
IDT89HPES16T7ZHBX datasheets

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Specifications of IDT89HPES16T7ZHBX

Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names89HPES16T7ZHBX
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IDT 89HPES16T7 Data Sheet
Signal
CCLKDS
CCLKUS
MSMBSMODE
P01MERGEN
PERSTN
RSTHALT
SWMODE[2:0]
Signal
JTAG_TCK
JTAG_TDI
Type
Name/Description
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indi-
cates that a common clock is being used between the downstream device
and the downstream port.
I
Common Clock Upstream. When the CCLKUS pin is asserted, it indi-
cates that a common clock is being used between the upstream device and
the upstream port.
I
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 kHz. This value
may not be overridden.
I
Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low
internally via a 251K ohm resistor.
When this pin is low, port 0 is merged with port 1 to form a single x8 port.
The Serdes lanes associated with port 1 become lanes 4 through 7 of port
0. When this pin is high, port 0 and port 1 are not merged, and each oper-
ates as a single x4 port
I
Fundamental Reset. Assertion of this signal resets all logic inside
PES16T7 and initiates a PCI Express fundamental reset.
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES16T7 executes the reset procedure and remains in a reset state
with the Master and Slave SMBuses active. This allows software to read
and write registers internal to the device before normal device operation
begins. The device exits the reset state when the RSTHALT bit is cleared in
the SWCTL register by an SMBus master.
I
Switch Mode. These configuration pins determine the PES16T7 switch
operating mode. These pins should be static and not change after the
negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
Table 5 System Pins
Type
Name/Description
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
Table 6 Test Pins (Part 1 of 2)
7 of 33
March 25, 2008

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