ADMC200AP Analog Devices Inc, ADMC200AP Datasheet
ADMC200AP
Specifications of ADMC200AP
Related parts for ADMC200AP
ADMC200AP Summary of contents
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FEATURES Analog Input Block 11-Bit Resolution Analog-to-Digital (A/D) Converter 4 Single-Ended Simultaneously Sampled Analog Inputs 3.2 s Conversion Time/Channel 0 V–5 V Analog Input Range Internal 2.5 V Reference PWM Synchronized Sampling Capability 12-Bit PWM Timer Block Three-Phase Center-Based ...
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... Measurements made with external reference. 2 Tested with PWM Switching Frequency of 25 kHz. Specifications subject to change without notice 5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = DD 12.5 MHz – +85 C unless otherwise noted) A ADMC200AP Units 1 11 Bits 2 LSB max 2 LSB max 5 LSB max 4 ...
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Table I. Timing Specifications (V Number Symbol 1 t clk per 2 t clk pwh 3 t clk pwl 4 t csb_wrb addr_wrb data_wrb wrb_data wrb_addr hd 9 ...
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... Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality Figure 4. Read Cycle Timing Diagram Part DD Number DD DD ADMC200AP DD DD –4– ORDERING GUIDE Temperature Package Package Range Description Option – +85 C 68-Lead PLCC P-68A WARNING! ESD SENSITIVE DEVICE REV. B ...
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Pin Mnemonic Type Description 1 D9 BIDIR Data Bit 9 2 D10 BIDIR Data Bit 10 3 D11 BIDIR Data Bit 11, MSB 4– Connect 10 V SUP +5 V Digital Power Supply I/P Address ...
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ADMC200 ANALOG INPUT BLOCK The ADMC200 contains an 11-bit resolution, successive approxi- mation analog-to-digital (A/D) converter with twos complement output data format. The analog input range is 2 V–5 V) with a 2.5 V offset as defined by ...
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PWMTM register value. Note: Desired Pulse Density = (PWMCHx register)/( PWMTM register). The beginning of each PWM cycle is marked by the PWMSYNC signal. New values of ...
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ADMC200 Stationary Reference Frame Reference Frame Figure 9. Forward Park Transformation 120 V x Equivalent Three-Phase Stator Two-Phase Voltage Figure 10. Forward Clarke Transformation Operating/Using the Vector Transformation Block After powering up the ...
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When an interrupt occurs, the user must check Bit 1 of the system status register, SYSSTAT, to determine if the vector transformation block was the source of the interrupt. During the vector transformation, the transformation registers must not be ...
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ADMC200 ADDRESS BUS A0–A13 ADDRESS DECODE ADSP-2101/ DMS EN ADSP-2105/ ADSP-2115–20MHz IRQ2 ADSP-2171–10MHz RD ADSP-2181–10MHz WR CLKOUT D0–D23 DATA BUS *NOTE: BY MAPPING THE ADMC200 DATA BUS TO THE TWELVE HIGHEST BITS OF THE ADSP DATA BUS, FULL-SCALE OUTPUTS FROM ...
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Name ID/PHV1/VX IQ/PHV2 IX/PHV3 IY/VY ADCV ADCW ADCAUX ADCU SYSCTRL SYSSTAT DESCRIPTION OF THE REGISTERS All unspecified register locations are reserved. SYSCTRL System Control Register (See Table V and VI) SYSSTAT System Status Register (See Table VII) ADCU These registers ...
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ADMC200 IRQ Pin Format—Edge or Level Interrupt Selection. Bit 8 If Bit 8 is set to 0, then an interrupt will cause a pulse of one system clock to be generated on the IRQ pin. If Bit 8 is set ...