ADMC200AP Analog Devices Inc, ADMC200AP Datasheet - Page 7

• Manufacturer Part Number: ADMC200AP
• Description: IC MOTION CO-PROC 12.5MHZ 68PLCC
• Manufacturer: Analog Devices Inc

Specifications of ADMC200AP

• Rohs Status: RoHS non-compliant
• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC

REV. B
desired on-time and their values would be calculated as a ratio
of the PWMTM register value. Note: Desired Pulse Density =
(PWMCHx register)/( PWMTM register).
The beginning of each PWM cycle is marked by the PWMSYNC
signal. New values of PWMCHA, PWMCHB and PWMCHC
must all be loaded into their respective registers at least four sys-
tem clock cycles before the beginning of a new PWM cycle. All
three registers must be updated for any of them to take effect.
New PWM on/off times are calculated during these four clock
cycles and therefore the PWMCHA, PWMCHB and PWMCHC
registers must be loaded before this time. If this timing require-
ment is not met, then the PWM outputs may be invalid during
the next PWM cycle.
PWM Example
The following example uses a system clock speed of 10 MHz.
The desired PWM master switching frequency is 8 kHz and the
desired on-time for the timers A, B and C are 25%, 50% and
10% respectively. The values for the PWMCHA, PWMCHB,
and PWMCHC registers must be calculated as ratios of the
PWMTM register (1250 in this example). To achieve these
duty cycles, load the PWMCHA register with 313 (1250
0.25), PWMCHB with 625 (1250 0.5) and PWMCHC with
125 (1250
Programmable Deadtime
With perfectly complemented PWM drive signals and nonideal
switching characteristics of the power devices, both transistors
in a particular leg might be switched on at the same time, result-
ing in either a power supply trip, inverter trip or device destruc-
tion. In order to prevent this, a delay must be introduced
between the complemented signal edges. For example, the ris-
ing edge of AP occurs before the falling edge of A, and the fall-
ing edge of the complemented A occurs after the rising edge of
A. This capability is known as programmable deadtime.
The ADMC200 programmable deadtime value is loaded into
the 7-bit PWMDT register, in which the LSB is set to zero in-
ternally, which means the deadtime value is always divisible by
two. With a 10 MHz system clock, the 0–126 range of values in
PWMDT yield a range of deadtime values from 0 s to 12.6 s
in 200 ns steps. Figure 6 shows PWM timer A with a program-
mable deadtime of PWMDT.
Pulse Deletion
The pulse deletion feature prevents a pulse from being gener-
ated when the user-specified duty cycle results in a pulse dura-
tion shorter than the user-specified deletion value. The pulse
deletion value is loaded into the 7-bit register PWMPD. When
the user-specified on-time for a channel would result in a calcu-
lated pulsewidth less than the value specified in the PWMPD
register, then the PWM outputs for that channel would be set to
Figure 6. Programmable Deadtime Example
AP
A
0.1).
PWMCHA + PWMDT
PWMCHA - PWMDT
PWMTM
–7–
full off (0%) and its prime to full on (100%). This is valid for
A, AP, B, BP, C and CP. This feature would be used in an en-
vironment where the inverter’s power transistors have a mini-
mum switching time. If the user-specified duty cycle would
result in a pulse duration shorter than the minimum switching
time of the transistors, then pulse deletion should be used to
prevent this occurrence. With a 10 MHz system clock, the 0–
127 range of values in PWMPD yield a range of deadtime values
from 0 s to 12.7 s in 100 ns steps.
External PWM Shutdown
There is an external input pin (STOP) to the PWM timers that
will disable all six outputs when it goes HIGH. When the STOP
pin goes HIGH, the PWM timer outputs will all go HIGH
within one system clock cycle. When the STOP pin goes
LOW, the PWM timer outputs are re-enabled within one system
clock cycle. If external PWM shutdown isn’t required, tie the
STOP pin LOW.
VECTOR TRANSFORMATION BLOCK OVERVIEW
The Vector Transformation Block performs both Park and
Clarke coordinate transformations to control a three-phase
motor (Permanent Magnet Synchronous Motor or Induction
Motor) via independent control of the decoupled rotor torque
and flux currents. The Park and Clarke transformations combine
to convert three-phase stator current signals into two orthogonal
rotor referenced current signals I
or magnetic field current and Iq represents the torque generat-
ing current. The I
processor’s motor torque control algorithm to calculate the
required direct V
motor. The forward Park and Clarke transformations are used
to convert the V
frame to three phase voltage signals (U, V, W) in the stator
reference frame. These are then scaled by the processor and
written to the ADMC200’s PWM registers in order to drive the
inverter. The figures below illustrate the Clarke and Park Trans-
formations respectively.
I
y
120
Reference Frame
Figure 7. Reverse Clarke Transformation
Figure 8. Reverse Park Transformation
Stator Currents
I
w
I
v
Rotating
Three-Phase
d
d
and V
and quadrature V
d
120
120
and I
I
x
q
voltage signals in the rotor reference
q
current signals are used by the
I
u
d
and I
Two-Phase Currents
q
voltage components for the
Reference Frame
q
I
. I
Stationary
Equivalent
y
d
represents the flux
ADMC200
90
I
I
d
q
ROTOR
REFERENCE
FRAME AXIS
I
x