IC MOTION CO-PROC 25MHZ 68PLCC

ADMC201AP

Manufacturer Part NumberADMC201AP
DescriptionIC MOTION CO-PROC 25MHZ 68PLCC
ManufacturerAnalog Devices Inc
ADMC201AP datasheet
 


Specifications of ADMC201AP

Rohs StatusRoHS non-compliantApplications*
Mounting TypeSurface MountPackage / Case68-PLCC
Operating Temperature (min)-40COperating Temperature (max)85C
Operating Temperature ClassificationIndustrialMountingSurface Mount
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FEATURES
Analog Input Block
11-Bit Resolution Analog-to-Digital (A/D) Converter
7 Single-Ended (SE) Analog Inputs
4 Simultaneously Sampled Analog Inputs
Expansion with 4 Multiplexed Inputs
3.2 s Conversion Time/Channel
0 V–5 V Analog Input Range
Internal 2.5 V Reference
PWM Synchronized Sampling Capability
12-Bit PWM Timer Block
Three-Phase Center-Based PWM
1.5 kHz–25 kHz PWM Switching Frequency Range
Programmable Deadtime
Programmable Pulse Deletion
PWM Synchronized Output
External PWM Shutdown
Vector Transformation Block
12-Bit Vector Transformations
Forward and Reverse Clarke Transformations
Forward and Reverse Park Rotations
2.9 s Transformation Time
Programmable Digital I/O Port
6-Bit Configurable Digital I/O
Change of State Interrupt Support
DSP & Microcontroller Interface
12 Bit Memory Mapped Registers
Twos Complement Data Format
6.25 MHz to 25 MHz Operating Clock Range
68-Pin PLCC Package
Single 5 V DC Power Supply
Industrial Temperature Range
GENERAL DESCRIPTION
The ADMC201 is a motion coprocessor that can be used with
either microcontrollers or digital signal processors (DSP). It
provides the functionality that is required to implement a digital
control system. In a typical application, the DSP or micro-
controller performs the control algorithms (position, speed,
torque and flux loops) and the ADMC201 provides the neces-
sary motor control functions: analog current data acquisition,
vector transformation, digital inputs/outputs, and PWM drive
signals.
PRODUCT HIGHLIGHTS
Simultaneous Sampling of Four Inputs
A four channel sample and hold amplifier allows three-phase
motor currents to be sampled simultaneously, reducing errors
from phase coherency. Sample and hold acquisition time is
1.6 s and conversion time per channel is 3.2 s (using a 12.5 MHz
system clock).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Motion Coprocessor
FUNCTIONAL BLOCK DIAGRAM
D0–D11
RESET
WR
EMBEDDED
A0–3
CONTROL
RD
SEQUENCER
CS
IRQ
CLK
INTERNAL
REFOUT
REFERENCE
REFIN
CONVST
11-BIT
U
A/D
V
CONVERTER
W
AUX
AUX0
MULTIPLEXER
AUX1
EXPANSION
AUX2
BLOCK
AUX3
PWMSYNC
A
AP
B
12-BIT
PWM TIMER
BP
BLOCK
C
CP
STOP
Flexible Analog Channel Sequencing
The ADMC201 supports acquisition of 2, 3, or 4 channels per
group. Converted channel results are stored in registers and
the data can be read in any order. The sampling and conversion
time for two channels is 8 s, three channels is 11.2 s, and four
channels is 14.4 s (using a 12.5 MHz system clock).
Embedded Control Sequencer
The embedded control sequencer off-loads the DSP or micro-
processor, reducing the instructions required to read analog
input channels, control PWM timers and perform vector trans-
formations. This frees the host processor for performing control
algorithms.
Fast DSP/Microprocessor Interface
The high speed digital interface allows direct connection to 16-bit
digital signal processors and microprocessors. The ADMC201
has 12 bit memory mapped registers with twos complement
data format and can be mapped directly into the data memory
map of a DSP. This allows for a single instruction read and write
interface.
Integration
The ADMC201 integrates a four channel simultaneous sampling
analog-to-digital converter, four channel analog multiplexer,
analog reference, vector transformation, six digital inputs/outputs,
and three-phase PWM timers into a 68-pin PLCC. Integration
reduces cost, board space, power consumption, and design and
test time.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
ADMC201
DATABUS
CONTROL BUS
CONTROL
REGISTERS
VECTOR
TRANSFORMATION
BLOCK
PROG.
DIGITAL
I/O
PIO 0–5
PORT
© Analog Devices, Inc., 2000

ADMC201AP Summary of contents

  • Page 1

    FEATURES Analog Input Block 11-Bit Resolution Analog-to-Digital (A/D) Converter 7 Single-Ended (SE) Analog Inputs 4 Simultaneously Sampled Analog Inputs Expansion with 4 Multiplexed Inputs 3.2 s Conversion Time/Channel 0 V–5 V Analog Input Range Internal 2.5 V Reference PWM ...

  • Page 2

    ... Measurements made with external reference. 2 Tested with PWM Switching Frequency of 25 kHz. Specifications subject to change without notice 5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = 12.5 MHz – +85 C unless otherwise noted) A ADMC201AP Units 1 11 Bits 2 LSB max 2 LSB max 5 LSB max ...

  • Page 3

    Table I. Timing Specifications (V Number Symbol 1 t clk per 2 t clk pwh 3 t clk pwl 4 t csb_wrb addr_wrb data_wrb wrb_data wrb_addr hd 9 ...

  • Page 4

    ... Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality Figure 4. Read Cycle Timing Diagram Part DD Number DD DD ADMC201AP DD DD –4– ORDERING GUIDE Temperature Package Package Range Description Option – +85 C 68-Pin PLCC P-68A WARNING! ESD SENSITIVE DEVICE REV. B ...

  • Page 5

    Pin Mnemonic Type Description 1 D9 BIDIR Data Bit 9 2 D10 BIDIR Data Bit 10 3 D11 BIDIR Data Bit 11, MSB 4 PIO0 BIDIR Programmable Digital I/O Bit 0 5 PIO1 BIDIR Programmable Digital I/O Bit 1 6 ...

  • Page 6

    ADMC201 ANALOG INPUT BLOCK The ADMC201 contains an 11-bit resolution, successive approxi- mation analog-to-digital (A/D) converter with twos complement output data format. The analog input range is 2 V–5 V) with a 2.5 V offset as defined by ...

  • Page 7

    PWM TIMER BLOCK OVERVIEW The PWM timers have 12-bit resolution and support program- mable pulse deletion and deadtime. The ADMC201 generates three center-based signals A, B and C based upon user-supplied duty cycles values. The three signals are then complemented ...

  • Page 8

    ADMC201 VECTOR TRANSFORMATION BLOCK OVERVIEW The Vector Transformation Block performs both Park and Clarke coordinate transformations to control a three-phase motor (Permanent Magnet Synchronous Motor or Induction Motor) via independent control of the decoupled rotor torque and flux currents. The ...

  • Page 9

    Reverse Clarke Transformation The first operation is the Clarke transformation in which the three-phase motor current signals ( sine and cosine orthogonal signals (I and I x represent the equivalent currents in a two-phase ac machine and ...

  • Page 10

    ADMC201 INTERRUPT GENERATION There are three interrupt sources on the ADMC201 that may be independently enabled to generate interrupts. The first inter- rupt source is the Analog Input Block, which, if enabled, generates an interrupt at the end of conversion. ...

  • Page 11

    ADDRESS BUS A0–A15 ADDRESS DECODE IS EN TMS320C20 INTn TMS320C25 STRB TMS320C25-50 R/W CLKOUT1 D0–D15 DATA BUS Figure 12. TI Second Generation Devices TMS320C20/ C25/C25–50 In the case of the ADSP-2171/2181, the system clock is inter- nally scaled ...

  • Page 12

    ADMC201 Name RHO PHIP1/VD PHIP2/VQ PHIP3 RHOP PWMTM PWMCHA PWMCHB PWMCHC PWMDT PWMPD PIOCTRL PIODATA SYSCTRL Name ID/PHV1/VX IQ/PHV2 IX/PHV3 IY/VY ADCV ADCW ADCAUX ADCU PIODATA SYSCTRL SYSSTAT Table III. Write Registers Register Function 3 2 ...

  • Page 13

    Table V. System Control (SYSCTRL) Registers Bit Function 0 Auxiliary Channel Selection 1 Auxiliary Channel Selection 3 Enables U Channel Conversion (1 = Enable) Two-/Three-Phase Mode 4 Enables AUX Channel Conversion (0 = Disable Enable) 5 Divide External ...

  • Page 14

    ADMC201 Table VIII. System Status Register (SYSSTAT) Bit Function 0 A/D Conversion Completion Interrupt (1 = True) 1 Vector Transformation Completion Interrupt (1 = True) 2 Digital I/O Change of State Interrupt (1 = True) 4 Rotation Results are Valid ...

  • Page 15

    PIN 1 IDENTIFIER TOP VIEW (PINS DOWN 0.954 (24.23) 0.950 (24.13) REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Plastic Leaded Chip Carrier (P-68A) 0.175 (4.45) 0.169 (4.29) SQ ...