IC SWITCH 10/100 3PORT 128PQFP

KS8993M

Manufacturer Part NumberKS8993M
DescriptionIC SWITCH 10/100 3PORT 128PQFP
ManufacturerMicrel Inc
KS8993M datasheets
 


Specifications of KS8993M

Applications*Mounting TypeSurface Mount
Package / Case128-MQFP, 128-PQFPNumber Of Primary Switch Ports3
Internal Memory Buffer Size32Operating Supply Voltage (typ)1.8/2.5/3.3V
Fiber SupportYesIntegrated Led DriversYes
Phy/transceiver InterfaceMII/SNIPower Supply TypeAnalog/Digital
Package TypePQFPData Rate (typ)10/100Mbps
Vlan SupportYesOperating Temperature (max)70C
Operating Temperature (min)0CPin Count128
MountingSurface MountJtag SupportNo
Operating Supply Voltage (max)1.89/3.465VOperating Supply Voltage (min)1.71/3.135V
Power Dissipation800mWSupply Current0.1/0.19A
Operating Temperature ClassificationCommercialData Rate100Mbps
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With576-1013 - BOARD EVAL EXPERIMENT KS8993M
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General Description
The KS8993M, a highly integrated Layer 2 managed
switch, is designed for low port count, cost-sensitive
10/100 Mbps switch systems. It offers an extensive
feature set that includes tag/port-based VLAN,
quality of service (QoS) priority, management,
management information base (MIB) counters,
MII/SNI,
and
CPU
control/data
effectively address both current and emerging Fast
Ethernet applications.
___________________________________________________________________________________________________
Functional Diagram
AUTO
MDI/MDI-X
AUTO
MDI/MDI-X
MII/SNI
SPI
MIIM
SMI
I 2 C
P1 LED[3:0]
P2 LED[3:0]
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
April 2005
The KS8993M contains two 10/100 transceivers with
patented mixed-signal low-power technology, three
media access control (MAC) units, a high-speed
non-blocking switch fabric, a dedicated address
lookup engine, and an on-chip frame buffer memory.
Both PHY units support 10BASE-T and 100BASE-
TX. In addition, one of the PHY unit supports
interfaces
to
100BASE-FX.
The KS8993ML is the single supply version with all
the identical rich features of the KS8993M.
10/100
10/100
T/TX/FX
MAC1
PHY 1
10/100
10/100
T/TX
MAC2
PHY 2
10/100
MAC3
SNI
SPI
Control
Registers
LED
Drivers
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
1
KS8993M/ML/MI
Integrated 3-Port 10/100 Managed
Switch with PHYs
Rev 1.04
1KLook-Up
Engine
Queue
Manageme nt
Buffer
Manageme nt
Frame
Buffers
MIB
Counters
EEP ROM
Interface
Strap-In
Configuration Pins
M9999-041205

KS8993M Summary of contents

  • Page 1

    ... Both PHY units support 10BASE-T and 100BASE- TX. In addition, one of the PHY unit supports interfaces to 100BASE-FX. The KS8993ML is the single supply version with all the identical rich features of the KS8993M. 10/100 10/100 T/TX/FX MAC1 ...

  • Page 2

    ... Unmanaged switch with future option to migrate to a managed solution – Single PHY alternative with future expansion option for two ports • Industrial Solutions – Applications requiring port redundancy and port monitoring – Sensor devices in redundant ring topology Note: 1. The cost and time of PCB re-spin. 2 KS8993M/ML/ +85 C M9999-041205 ...

  • Page 3

    ... Micrel, Inc. Ordering Information Part Number Temperature Range o o KS8993M KS8993ML KS8993MI – + KSZ8993M KSZ8993ML April 2005 Package 128-Pin PQFP 128-Pin PQFP 128-Pin PQFP 128-Pin PQFP, Lead-free 128-Pin PQFP, Lead-free 3 KS8993M/ML/MI M9999-041205 ...

  • Page 4

    ... Updated KS8993MI availability to from Q1 2004. Added KS8993ML to General Description (page 1) and to the Functional Description. Updated Part Ordering Information table. Updated pin description for pin 22 to the following For KS8993M, this is an input power pin for the 1.8V digital DDC core _1V8: For KS8993ML, this is an 1.8V output power pin to OUT supply the KS8993ML’ ...

  • Page 5

    ... Port Mirroring Support........................................................................................................................................................35 IEEE 802.1Q VLAN Support ................................................................................................................................................35 QoS Priority Support...........................................................................................................................................................36 Rate Limiting Support .........................................................................................................................................................38 Configuration Interface ....................................................................................................................................................... Master Serial Bus Configuration .............................................................................................................................. Slave Serial Bus Configuration ................................................................................................................................39 SPI Slave Serial Bus Configuration ...............................................................................................................................39 Loopback Support...............................................................................................................................................................43 MII Management (MIIM) Registers .......................................................................................................44 Register 0: MII Basic Control..........................................................................................................................................45 April 2005 5 KS8993M/ML/MI M9999-041205 ...

  • Page 6

    ... Register 25 (0x19): Port 1 Control 9...............................................................................................................................58 Register 41 (0x29): Port 2 Control 9...............................................................................................................................58 Register 57 (0x39): Port 3 Control 9...............................................................................................................................58 Register 26 (0x1A): Port 1 Control 10 ............................................................................................................................58 Register 42 (0x2A): Port 2 Control 10 ............................................................................................................................58 Register 58 (0x3A): Port 3 Control 10 ............................................................................................................................58 Register 27 (0x1B): Port 1 Control 11 ............................................................................................................................58 Register 43 (0x2B): Port 2 Control 11 ............................................................................................................................58 April 2005 6 KS8993M/ML/MI M9999-041205 ...

  • Page 7

    ... SPI Timing….…………………………………………………………………………………………………………………………...77 Input Timing ...................................................................................................................................................................80 Output Timing.................................................................................................................................................................81 Reset Timing........................................................................................................................................................................82 Selection of Isolation Transformers....................................................................................................84 Selection of Reference Crystal ............................................................................................................84 Package Information.............................................................................................................................85 April 2005 7 KS8993M/ML/MI M9999-041205 ...

  • Page 8

    ... Figure 4. Destination Address Lookup Flow Chart, Stage 1 ..............................................................................................................27 Figure 5. Destination Address Resolution Flow Chart, Stage 2 ........................................................................................................28 Figure 6. 802.1p Priority Field Format ..................................................................................................................................................37 Figure 7. KS8993M EEPROM Configuration Timing Diagram ............................................................................................................38 Figure 8. SPI Write Data Cycle...............................................................................................................................................................41 Figure 9. SPI Read Data Cycle ...............................................................................................................................................................41 Figure 10. SPI Multiple Write..................................................................................................................................................................41 Figure 11 ...

  • Page 9

    ... P2LED3 P2LED2 P2LED1 P2LED0 Notes: LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P2LED3 is pin 20. During reset, P2LED[2:0] are inputs for internal testing. Gnd Digital ground 9 KS8993M/ML/MI [LEDSEL1, LEDSEL0] [0, 0] [0, 1] — — Link/Act 100Link/Act Full duplex/Col 10Link/Act Speed Full duplex ...

  • Page 10

    ... Opd Port 2 LED indicator Note: Internal pull-down is weak; it will not turn ON the LED. See description in pin 4. Gnd Digital ground For KS8993M, this is an input power pin for the 1.8V DDC digital core For KS8993ML, this is a 1.8V output power pin to OUT_1V8 supply the KS8993ML’ ...

  • Page 11

    ... Ipu Chip power-down input (active low) Gnd Analog ground P 1.8V analog V DD Gnd Analog ground I Factory test pin - float for normal operation I Factory test pin - float for normal operation Gnd Analog ground P 1.8V analog Fiber signal detect/factory test pin 11 KS8993M/ML/MI M9999-041205 ...

  • Page 12

    ... connect. Note: Clock is +/- 50ppm for both crystal and oscillator. Ipu Hardware reset pin (active low) Ipd Half-duplex backpressure 1 = enable 0 = disable Ipd Special Mac-mode In this mode, the switch will do faster back-offs than normal enable 0 = disable 12 KS8993M/ML/MI M9999-041205 ...

  • Page 13

    ... Strap option: Switch MII (default) = 100Mbps mode PU = 10Mbps mode Ipd/O Switch MII receive bit 0 Strap option: switch will accept packet size (default) = 1536 bytes (inclusive 1522 bytes (tagged), 1518 bytes (untagged) Ipd/O Switch MII collision detect Ipd/O Switch MII carrier sense 13 KS8993M/ML/MI M9999-041205 ...

  • Page 14

    ... C master/slave mode: serial data input/output See description in pins 100 and 101. Ipu SPI slave mode: chip select (active low) When SPIS_N is high, the KS8993M is deselected and SPIQ is held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. See description in pins 100 and 101. ...

  • Page 15

    ... SCL SDA SPIS_N [PS1, PS0] = [1, 1] – SMI-mode In this mode, the KS8993M provides access to all its internal 8 bit registers through its MDC and MDIO pins. Note: When (PS1, PS0) ≠ (1,1), the KS8993M provides access to its 16 bit MIIM registers through its MDC and MDIO pins. ...

  • Page 16

    ... Select transmit queue split on port split split The split sets up high and low priority queues. Packet priority classification is done on ingress ports, via port-based, 802.1p or TOS based scheme. The priority enabled queuing on port 3 is set by P3_TXQ2. Ipd = Input w/ internal pull-down. 16 KS8993M/ML/MI M9999-041205 ...

  • Page 17

    ... Ipd Enable tag insertion on port 2 egress 1 = enable 0 = disable All packets transmitted from port 2 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port’s default tag. 17 KS8993M/ML/MI M9999-041205 ...

  • Page 18

    ... Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. Ipd Scan Test Enable For normal operation, pull-down this pin to ground. Ipd Scan Test Scan Mux Enable For normal operation, pull-down this pin to ground. 18 KS8993M/ML/MI M9999-041205 ...

  • Page 19

    ... P3_TXQ2 P2_TXQ2 P1_TXQ2 P3_PP P2_PP P1_PP P3_TAGINS P2_TAGINS P1_TAGINS DGND VDDC P3_TAGRM P2_TAGRM P1_TAGRM TESTEN SCANEN April 2005 128-Pin PQFP (Top View) 19 KS8993M/ML/MI AGND VDDAP AGND ISET TEST2 TEST1 AGND VDDA TXP2 TXM2 AGND RXP2 RXM2 VDDARX VDDATX TXM1 TXP1 AGND ...

  • Page 20

    ... On the media side, the KS8993M supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports, and 100BASE-FX on PHY port 1. The KS8993M can be used as a media converter. The KS8993ML is the single supply version with all the identical rich features of the KS8993M. In the KS8993ML version, pin number 22 provides 1.8V output power to the KS8993ML’ the Pin Description table for information about pin 22 (Pin Description and I/0 Assignment) ...

  • Page 21

    ... An FEF occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KS8993M detects a FEF when its FXSD1 input is between 1.0V and 1.8V. When an FEF occurs, the transmission side signals the other end of the link by sending 84 1’s followed by a zero in the idle period between frames. ...

  • Page 22

    ... Power Management The KS8993M features a per-port power down mode. To save power, the user can power down ports that are not in use by setting the port control registers, or MII control registers. In addition, there is a full chip power down mode ...

  • Page 23

    ... NIC card (MDI) and a switch, or hub (MDI-X). 10/100 Ethernet Media Dependent Interface Transmit Pair Receive Pair Modular Connector (RJ-45) NIC April 2005 Media Dependent Interface 1 2 Straight 3 Cable Figure 1. Typical Straight Cable Connection 23 KS8993M/ML/MI 10/100 Ethernet 1 Receive Pair Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) M9999-041205 ...

  • Page 24

    ... If auto negotiation is not supported or the link partner to the KS8993M is forced to bypass auto negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...

  • Page 25

    ... Ye s Bypass Auto Negotiation and Set Link Mode April 2005 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes Link Mode Set Figure 3. Auto Negotiation and Parallel Operation 25 KS8993M/ML/MI Listen for 10BASE-T Link Pulses No M9999-041205 ...

  • Page 26

    ... Global Register 3 (0x03). Forwarding The KS8993M will forward packets using the algorithm that is depicted in the following flowcharts. Figure 4 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLA processes to come up with “ ...

  • Page 27

    ... Search VLAN table NO VLAN ID - Ingress VLAN filtering Valid? - Discard NPVID check YES FOUND Search Static This search is based on Table DA or DA+FID NOT FOUND FOUND This search is based on Dynamic Table DA+FID Search NOT FOUND Search complete. Get PTF1 from VLAN Table PTF1 27 KS8993M/ML/MI M9999-041205 ...

  • Page 28

    ... Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. The KS8993M will intercept these packets and perform the appropriate actions. 3. "Local" packets. Based on destination address (DA) lookup. If the destination port from the lookup table matches the port where the packet was from, the packet is defined as " ...

  • Page 29

    ... If a transmit packet experiences collisions after 512 bit times of the transmission, the packet will be dropped. Illegal Frames The KS8993M discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in Global Register 4 (0x04). For special applications, the KS8993M can also be programmed to accept frames up to 1916 bytes in the same global register ...

  • Page 30

    ... The MII is specified by the IEEE 802.3 standards committee and provides a common interface between physical layer and MAC layer devices. The MII Interface provided by the KS8993M is connected to the device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for reception. The following table describes the signals used in the MII interface ...

  • Page 31

    ... MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8993M has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8993M has an MTXER pin, it should be tied low. ...

  • Page 32

    ... Table 6. Serial Management Interface (SMI) Frame Format For the KS8993M, SMI register access is selected when bit 2 of the PHY address is set to ‘1’. PHY address bits [1:0] are not defined for SMI register access, and hence can be set to either 0’s or 1’s in read/write operation. ...

  • Page 33

    ... Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0” April 2005 Only packets to the processor are forwarded. Learning is disabled. Only packets to and from the processor are forwarded. Learning is disabled. Only packets to and from the processor are forwarded. Learning is enabled. 33 KS8993M/ML/MI M9999-041205 ...

  • Page 34

    ... TPID (tag protocol identifier, 0x8100) + TCI. The STPID is only seen and used by the port 3 interface, which should be connected to a processor. The KS8993M uses a non-zero “port mask” to bypass the lookup result and override any port setting, regardless of port states (disable, blocking, listening, learning). ...

  • Page 35

    ... A packet received on port 1 is destined to port 2 after the internal lookup. The KS8993M will forward the packet to both port 2 and port 3. The KS8993M can optionally forward even “bad” received packets to the “sniffer port”. ...

  • Page 36

    ... Yes Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KS8993M. These features can be set on a per port basis, and are defined in register 18, bit 6 and bit 5, respectively for port 1. QoS Priority Support This feature provides Quality of Service (QoS) for applications, such as VoIP and video conferencing ...

  • Page 37

    ... The CRC is recalculated for both tag insertion and tag removal. 802.1p Priority Field Re-mapping is a QoS feature that allows the KS8993M to set the “User Priority Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the ingress port, the packet’ ...

  • Page 38

    ... Rate limiting is supported in both priority and non-priority environment. The rate limit starts from 0 kbps and goes up to the line rate in steps of 32 kbps. The KS8993M uses “one second” as the rate limiting interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. On the “ ...

  • Page 39

    ... Enable I C slave mode by setting the KS8993M strap-in pins PS[1:0] (pins 100 and 101, respectively) to “01”. 2. Power up the board and assert reset to the KS8993M. After reset, the “Start Switch” bit (register 1 bit 0) will be set to ‘0’. 3. Configure the desired register settings in the KS8993M, using the I 4. Read back and verify the register settings in the KS8993M, using the I 5. Write a ‘ ...

  • Page 40

    ... The KS8993M internal address counter will increment automatically to the next byte (next register) after the write. The next byte that is sent from the master device to the KS8993M SDA input pin will be written to the next register address. SPI multiple write will continue until the SPI master device terminates it by de-asserting the SPIS_N signal to the KS8993M ...

  • Page 41

    ... SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ Byte 2 April 2005 WRITE ADDRESS Figure 8. SPI Write Data Cycle READ ADDRESS Figure 9. SPI Read Data Cycle WRITE ADDRESS Byte 3 ... Figure 10. SPI Multiple Write 41 KS8993M/ML/ WRITE DATA READ DATA Byte Byte N M9999-041205 ...

  • Page 42

    ... Micrel, Inc. SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID SPIQ Byte 2 April 2005 READ ADDRESS Byte 3 Figure 11. SPI Multiple Read 42 KS8993M/ML/ Byte Byte N M9999-041205 ...

  • Page 43

    ... Micrel, Inc. Loopback Support The KS8993M provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100BASE-TX, and the “Priority Buffer reserve” bit needs to be set to 48 pre- allocated buffers per output queue. The latter is required to prevent loopback packet drops and is achieved by setting register 4 bit 0 to ‘ ...

  • Page 44

    ... Normal operation NOT SUPPORTED =1, Restart auto-negotiation =0, Normal operation =1, Full duplex =0, Half duplex NOT SUPPORTED =1, Force MDI (transmit on RXP / RXM pins) =0, Normal operation (transmit on TXP / TXM pins) 44 KS8993M/ML/ and SMI Default Reference 0 0 Reg. 29, bit 0 Reg. 45, bit 0 0 Reg. 28, bit 6 Reg. 44, bit 6 ...

  • Page 45

    ... No far end fault detected =1, Auto-negotiation capable =0, Not auto-negotiation capable =1, Link is up =0, Link is down NOT SUPPORTED =0, Not extended register capable Description High order PHYID bits Description Low order PHYID bits 45 KS8993M/ML/MI Default Reference 0 Reg. 29, bit 2 Reg. 45, bit 2 0 Reg. 29, bit 4 0 Reg. 29, bit 6 Reg. 45, bit 6 0 Reg ...

  • Page 46

    ... Do not advertise 10 half duplex ability 802.3 Description NOT SUPPORTED NOT SUPPORTED NOT SUPPORTED Link partner pause capability Link partner 100 full capability Link partner 100 half capability Link partner 10 full capability Link partner 10 half capability 46 KS8993M/ML/MI Default Reference Reg. 28, bit 4 Reg. 44, bit Reg ...

  • Page 47

    ... Description TOS Priority Control Registers Switch Engine’s MAC Address Registers Indirect Access Control Registers Indirect Data Registers Digital Testing Status Registers Digital Testing Control Registers Analog Testing Control Registers Analog Testing Status Register Description Chip family 47 KS8993M/ML/MI Default 0x93 M9999-041205 ...

  • Page 48

    ... After an age cycle is complete, the age logic will return to normal aging (about 200 sec). Note: If any port is unplugged, all addresses will be automatically aged out. 48 KS8993M/ML/MI Default 0x0 - - Default 0x0 0x4 ...

  • Page 49

    ... Note: Port mirroring is not supported if this bit is set to “0” “Broadcast Storm Protection” does not include multicast packets. Only DA = FFFFFFFFFFFF packets will be regulated “Broadcast Storm Protection” includes DA = FFFFFFFFFFFF and DA[40 packets carrier sense based backpressure is selected = 0, collision based backpressure is selected 49 KS8993M/ML/MI Default SMAC (pin 69) value during reset ...

  • Page 50

    ... IGMP snoop is enabled. All the IGMP packets will be forwarded to the Switch MII port. =0, IGMP snoop is disabled always deliver high priority packets first 01 = deliver high/low packets at ratio 10 deliver high/low packets at ratio 5 deliver high/low packets at ratio 2/1 50 KS8993M/ML/MI Default 1 SMAC (pin 69) value during reset. 0 SMRXD0 ...

  • Page 51

    ... MII interface full-duplex mode enable full-duplex flow control on Switch MII interface disable full-duplex flow control on Switch MII interface the switch interface is in 10Mbps mode = 0, the switch interface is in 100Mbps mode 51 KS8993M/ML/MI Default 0 Default 0 Pin SMRXD2 strap option. Pull-down(0): Full-duplex ...

  • Page 52

    ... The period is 67ms for 100BT or 500ms for 10BT. The default is 1%. Description Reserved Description Reserved Description Reserved 52 KS8993M/ML/MI Default 0 000 Default 0x63 Default 0x4E Default 0x24 Default ...

  • Page 53

    ... PxLED2 LINK/ACT PxLED1 FULL_DPX/COL PxLED0 SPEED [LEDSEL1, LEDSEL0] [1, 0] PxLED3 ACT PxLED2 LINK PxLED1 FULL_DPX/COL PxLED0 SPEED LEDSEL0 is external strap-in pin #70. LEDSEL1 is external strap-in pin #23. 53 KS8993M/ML/MI Default 0 LEDSEL0 pin value during reset. [0, 1] ------ 100LINK/ACT 10LINK/ACT FULL_DPX [1, 1] ------ ------ ------ ------ 0 Default 0x00 ...

  • Page 54

    ... The switch will not add tags to packets already tagged. The tag inserted is the ingress port’s “port VID” disable tag insertion 54 KS8993M/ML/MI Default 0 0 Pin value during reset: P1_1PEN (port ...

  • Page 55

    ... Define the port’s “ egress port VLAN membership. Bit 2 stands for port 3, bit 1 for port 2 bit 0 for port 1. The Port can only communicate within the membership. A ‘1’ includes a port in the membership, a ‘0’ excludes a port from membership. 55 KS8993M/ML/MI Default Pin value during reset: P1_TAGRM (port 1) P2_TAGRM ...

  • Page 56

    ... Description Port’s default tag, containing 7-5 : User priority bits 4 : CFI bit 3-0 : VID[11:8] 56 KS8993M/ML/MI Default Pin value during reset: For port 1, P1FFC pin For port 2, ...

  • Page 57

    ... Description This register along with port control 10, bits [3:0] form a 12-bits field to determine how many “32Kbps” high priority blocks can be received in a unit of 4Kbytes in a one second period). 57 KS8993M/ML/MI Default 0x01 Default 0x00 Default 0x00 ...

  • Page 58

    ... KS8993M/ML/MI Default 0x00 Default 0x0 0x0 Default ...

  • Page 59

    ... Description = 0, disable auto negotiation, speed and duplex are decided by bit 6 and 5 of the same register auto negotiation forced 100BT disabled (bit forced 10BT disabled (bit 7) 59 KS8993M/ML/MI Default Default For port 1, P1ANEN pin value during reset ...

  • Page 60

    ... LEDx_1, LEDx_0, where “x” is the port number). These pins will be driven high if this bit is set to one normal operation = 1, disable port’s transmitter = 0, normal operation = 1, restart auto-negotiation = 0, normal operation 60 KS8993M/ML/MI Default For port 1, P1DPX pin value during reset. For port 2, P2DPX pin value during reset ...

  • Page 61

    ... Description = 1, MDI MDI = 1, AN done = 0, AN not done = 1, link good = 0, link not good = 1, link partner flow control (pause) capable = 0, link partner not flow control (pause) capable 61 KS8993M/ML/MI Default 0 Note: Only port 1 supports fiber. This bit is applicable to port 1 only For port 2, ...

  • Page 62

    ... KS8993M/ML/MI Default Default ...

  • Page 63

    ... Register 103 (0x67): TOS Priority Control Register 7 Bit Name R/W 7-0 DSCP[7:0] R/W April 2005 Description Description Description Description Description Description Description Description 63 KS8993M/ML/MI Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 M9999-041205 ...

  • Page 64

    ... Register 108 (0x6C): MAC Address Register 4 Bit Name R/W 7-0 MACA[15:8] R/W Register 109 (0X6D): MAC Address Register 5 Bit Name R/W 7-0 MACA[7:0] R/W April 2005 Description Description Description Description Description Description 64 KS8993M/ML/MI Default 0x00 Default 0x10 Default 0xA1 Default 0xFF Default 0xFF Default 0xFF M9999-041205 ...

  • Page 65

    ... Description Bit 7-0 of indirect address Description Bit 68-64 of indirect data Description Bit 63-56 of indirect data Description Bit 55-48 of indirect data Description Bit 47-40 of indirect data Description Bit 39-32 of indirect data 65 KS8993M/ML/MI Default 000 Default 0000_0000 Default 0_0000 Default 0000_0000 Default 0000_0000 ...

  • Page 66

    ... Registers 121 to 127 are Reserved. Static MAC Address Table The KS8993M has both a static and a dynamic MAC address table. When a destination address (DA) lookup is requested, both tables are searched to make a packet forwarding decision. When a SA lookup is requested, only the dynamic table is searched for aging, migration and learning purposes. The static DA lookup result will have precedence over the dynamic DA lookup result ...

  • Page 67

    ... R/W 48 bits MAC address nd Entry) th Entry) 67 KS8993M/ML/MI Default 000 0x0000_0000_0000 M9999-041205 ...

  • Page 68

    ... VID If 802.1Q VLAN mode is enabled, KS8993M will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The lookup process will start from the VLAN table lookup. If the VID is not valid, the packet will be dropped and no address learning will take place ...

  • Page 69

    ... Read reg. 120 (7-0) MIB (Management Information Base) Counters The KS8993M provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.” ...

  • Page 70

    ... The number of times a collision is detected later than 512 bit-times into the packet Number of PAUSE frames transmitted by a port Tx good broadcast packets (not including error broadcast or valid multicast packets) Tx good multicast packets (not including error multicast packets or valid broadcast packets) Tx good unicast packets 70 KS8993M/ML/MI M9999-041205 ...

  • Page 71

    ... R/W Description N/A Reserved RO Counter value Description TX packets dropped due to lack of resources TX packets dropped due to lack of resources TX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources 71 KS8993M/ML/MI Default N/A 0 M9999-041205 ...

  • Page 72

    ... A high performance SPI master is also recommended to prevent counters overflow. Per Port MIB counters are designed as “read clear.” That is, these counters will be cleared after they are read. “All Port Dropped Packet” MIB counters are not cleared after they are read. April 2005 72 KS8993M/ML/MI M9999-041205 ...

  • Page 73

    ... DDATX DDARX DDIO All Inputs –0.5V to 4.0V All Outputs –0.5V to 4.0V N/A N/A -55 ° 150 ° C Symbol Min 1.710V DDA DDAP DDC 3.135V DDATX DDARX DDIO θ KS8993M/ML/MI Typ Max 1.8V 1.890V 3.3V 3.465V 0 ° ° C/W M9999-041205 70 ° C 125 ° C ...

  • Page 74

    ... Electrical Characteristics V = xx; R =xx 25°C, bold values indicate –40°C< Parameter Supply Current (including TX output driver current, KS8993M device only) 100BASE-TX (analog core + PLL + digital core) 100BASE-TX (transceiver + digital I/O) 10BASE-T (analog core + PLL + digital core) 10BASE-T (transceiver + digital I/O) TTL Inputs ...

  • Page 75

    ... Peak Differential Output Voltage Jitters Added Rise/Fall Time Note: 1. Specification for packaged product only. April 2005 (1) Symbol Condition 5MHz square wave V sq 100 Ω termination on the differential V p output. 100 Ω termination on the differential output. 75 KS8993M/ML/MI Min Typ Max 400mV 2.3V + 3.5ns 25ns M9999-041205 ...

  • Page 76

    ... Figure 14. EEPROM Interface Output Timing Diagram Timing Parameter Description Clock cycle t cyc1 Setup time t s1 Hold time t h1 Output valid t ov1 April 2005 Figure 13. EEPROM Interface Input Timing Diagram Min 20 20 4096 Table 20. EEPROM Timing Parameters 76 KS8993M/ML/MI Typ Max 16384 4112 4128 M9999-041205 Unit ...

  • Page 77

    ... Micrel, Inc. SNI Timing Timing Parameter Description Clock cycle t cyc2 Setup time t s2 Hold time t h2 Output valid t ov2 April 2005 Figure 15. SNI Input Timing Diagram Figure 16. SNI Output Timing Diagram Min Typ 100 Table 21. SNI Timing Parameters 77 KS8993M/ML/MI Max Unit M9999-041205 ...

  • Page 78

    ... Clock cycle cyc3 100BASE-T tcyc3 (10BASE-T) Clock cycle 10BASE-T Setup time t s3 Hold time t h3 Output valid t ov3 April 2005 Figure 18. MAC-Mode MII Timing – Data Input to MII Min Table 22. MAC-Mode MII Timing Parameters 78 KS8993M/ML/MI Typ Max Unit 40 ns 400 M9999-041205 ...

  • Page 79

    ... Clock cycle (100BASE-T) 100BASE-T tcyc4 (10BASE-T) Clock cycle 10BASE-T ts4 Setup time th4 Hold time tov4 Output valid April 2005 Figure 20. PHY-Mode MII Timing – Data Input to MII Min Table 23. PHY-Mode MII Timing Parameters 79 KS8993M/ML/MI Typ Max Unit 40 ns 400 M9999-041205 ...

  • Page 80

    ... SPIS_N active old time SPIS_N inactive setup time SPIS_N deselect time Data input setup time Data input hold time Clock rise time Clock fall time Data input rise time Data input fall time Table 24. SPI Input Timing Parameters 80 KS8993M/ML/MI Min Max Units 5 MHz ...

  • Page 81

    ... April 2005 Figure 22. SPI Output Timing Description Clock frequency SPIQ hold time Clock low to SPIQ valid Clock high time Clock low time SPIQ rise time SPIQ fall time SPIQ disable time Table 25. SPI Output Timing Parameters 81 KS8993M/ML/MI Min Max Units 5 MHz ...

  • Page 82

    ... Micrel, Inc. Reset Timing As long as the stable supply voltages to reset high timing (minimum of10ms) are met, there is no power sequencing requirement for the KS8993M supply voltages (1.8V, 3.3 recommended to wait 100µsec after the de-assertion of reset before starting programming on the managed interface. ...

  • Page 83

    ... CPU/FPGA provides warm reset after power up also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. April 2005 Figure 24. Recommended Reset Circuit 83 KS8993M/ML/MI M9999-041205 ...

  • Page 84

    ... SI-46001 SI-50170 LF8505 LF-H41S H1102 H1260 HB726 LF-H41S Table 28. Qualified Single Port Magnetics Value 25.00000 ± Table 29. Typical Reference Crystal Characteristics 84 KS8993M/ML/MI Test Condition 100mV, 100kHz, 8mA 1MHz (min.) 0MHz – 65MHz Auto MDI-X Number of Port Yes 1 Yes 1 Yes 1 Yes 1 Yes ...

  • Page 85

    ... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. April 2005 128-Pin PQFP Package FAX: +1 (408) 474 1000 WEB: http:/www.micrel.com © 2003 Micrel, Incorporated. 85 KS8993M/ML/MI M9999-041205 ...