KS8993M Micrel Inc, KS8993M Datasheet - Page 14

• Manufacturer Part Number: KS8993M
• Description: IC SWITCH 10/100 3PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8993M

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Supply Voltage (min): 1.71/3.135V
• Power Dissipation: 800mW
• Supply Current: 0.1/0.19A
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1013 - BOARD EVAL EXPERIMENT KS8993M
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

Micrel, Inc.
April 2005
Note:
1. P = Power supply.
Pin Number
88
89
90
91
92
93
94
95
96
97
98
99
Gnd = Ground.
Ipu = Input w/ internal pull-up.
Ipd = Input w/ internal pull-down.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
Opu = Output w/ internal pull-up.
Pin Name
SCONF1
SCONF0
DGND
VDDC
PRSEL1
PRSEL0
MDC
MDIO
SPIQ
SCL
SDA
SPIS_N
Type
Ipd
Ipd
Gnd
P
Ipd
Ipd
Ipu
Ipu/O
Opu
Ipu/O
Ipu/O
Ipu
(1)
14
Description
Switch MII interface configuration
Digital ground
1.8V digital VDD
Priority select. Select queue servicing if using split queues.
Use the table below to select the desired servicing. Note that
this selection effects all split transmit queue ports in the same
way.
MII management interface: clock input
MII management interface: data input/output
Note: an external 4.7K pull-up is needed on this pin when it is
in use.
SPI slave mode: serial data output
See description in pins 100 and 101.
SPI slave mode / I
I
See description in pins 100 and 101.
SPI slave mode: serial data input
I
See description in pins 100 and 101.
SPI slave mode: chip select (active low)
When SPIS_N is high, the KS8993M is deselected and SPIQ
is held in high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
See description in pins 100 and 101.
2
2
(SCONF1, SCONF0)
(0,0)
(0,1)
(1,0)
(1,1)
(PRSEL1, PRSEL0)
(0,0)
(0,1)
(1,0)
(1,1)
C master mode: clock output
C master/slave mode: serial data input/output
2
C slave mode: clock input
Description
disable, outputs tri-stated
PHY mode MII
MAC mode MII
PHY mode SNI
Description
Transmit all high priority before low
priority
Transmit high priority and low priority at
10:1 ratio.
Transmit high priority and low priority at
5:1 ratio.
Transmit high priority and low priority at
2:1 ratio.
KS8993M/ML/MI
M9999-041205