KS8995MAI Micrel Inc, KS8995MAI Datasheet
KS8995MAI
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KS8995MAI Summary of contents
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KS8995MA General Description The KS8995MA is a highly integrated Layer 2 managed switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set such as tag/port-based VLAN, quality ...
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... FTTx customer premise equipment • Managed Media converter Ordering Information Part Number Temp. Range KS8995MA 0°C to +70°C 128-Pin PQFP KSZ8995MA 0°C to +70°C 128-Pin PQFP KS8995MAI –40°C to +85°C 128-Pin PQFP 2 Micrel, Inc. Package Lead Finish Standard Lead-Free Standard May 2005 ...
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KS8995MA Revision History Revision Date Summary of Changes 2.0 10/10/03 Created. 2.1 10/30/03 Editorial changes on electrical characteristics. 2.2 4/1/04 Editorial changes on the TTL input and output electrical characteristics. 2.3 1/19/05 Insert recommended reset circuit., Pg. 70. Editorial, Pg. ...
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KS8995MA Table of Contents System Level Applications ......................................................................................................................................... 7 Pin Description by Number ........................................................................................................................................ 9 Pin Description by Name .......................................................................................................................................... 15 Pin Configuration ...................................................................................................................................................... 21 Introduction ........................................................................................................................................................... 22 Functional Overview: Physical Layer Transceiver ............................................................................................... 22 100BASE-TX Transmit ........................................................................................................................................ 22 100BASE-TX ...
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KS8995MA Register Description ................................................................................................................................................. 39 Global Registers .................................................................................................................................................. 39 Register 0 (0x00): Chip ID0 ......................................................................................................................... 39 Register 1 (0x01): Chip ID1/Start Switch ..................................................................................................... 39 Register 2 (0x02): Global Control 0 ............................................................................................................. 40 Register 3 (0x03): Global Control 1 ............................................................................................................. 40 ...
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KS8995MA Register 112 (0x70): Indirect Data Register 8 ............................................................................................. 51 Register 113 (0x71): Indirect Data Register 7 ............................................................................................. 51 Register 114 (0x72): Indirect Data Register 6 ............................................................................................. 51 Register 115 (0x73): Indirect Data Register 5 ............................................................................................. 51 Register 116 (0x74): ...
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KS8995MA System Level Applications CPU WAN PHY & AFE (xDSL, CM...) May 2005 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SPI/GPIO SPI Ethernet MAC MII-SW Ethernet MAC Figure 1. Broadband Gateway SPI/GPIO ...
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KS8995MA M9999-051305 10/100 10/100 PHY 1 MAC 1 10/100 10/100 MAC 2 PHY 2 10/100 10/100 PHY 3 MAC 3 10/100 10/100 MAC 4 PHY 4 10/100 10/100 MAC 5 PHY 5 Figure 3. Standalone Switch 8 Micrel, Inc. 5-port ...
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KS8995MA Pin Description (by Number) Pin Number Pin Name Type 1 MDI-XDIS 2 GNDA Gnd 3 VDDAR 4 RXP1 5 RXM1 6 GNDA Gnd 7 TXP1 8 TXM1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA Gnd 13 TXP2 14 ...
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KS8995MA Pin Number Pin Name Type 31 VDDAR 32 RXP5 33 RXM5 34 GNDA Gnd 35 TXP5 36 TXM5 37 VDDAT 38 FXSD5 39 FXSD4 40 GNDA Gnd 41 VDDAR 42 GNDA Gnd 43 VDDAR 44 GNDA Gnd 45 MUX1 ...
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KS8995MA Pin Number Pin Name Type 61 PMRXDV Ipd/O 62 PMRXD3 Ipd/O 63 PMRXD2 Ipd/O 64 PMRXD1 Ipd/O 65 PMRXD0 Ipd/O 66 PMRXER Ipd/O 67 PCRS Ipd/O 68 PCOL Ipd/O 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 ...
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KS8995MA Pin Number Pin Name Type 82 SMRXD1 Ipd/O 83 SMRXD0 Ipd/O 84 SCOL Ipd/O 85 SCRS Ipd/O 86 SCONF1 87 SCONF0 88 GNDD 89 VDDC 90 LED5-2 Ipu/O 91 LED5-1 Ipu/O 92 LED5-0 Ipu/O 93 LED4-2 Ipu/O 94 LED4-1 ...
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KS8995MA Pin Number Pin Name Type 98 LED3-0 Ipu/O 99 GNDD Gnd 100 VDDIO 101 LED2-2 Ipu/O 102 LED2-1 Ipu/O 103 LED2-0 Ipu/O 104 LED1-2 Ipu/O 105 LED1-1 Ipu/O 106 LED1-0 Ipu/O 107 MDC 108 MDIO 109 SPIQ 110 SPIC/SCL ...
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KS8995MA Pin Number Pin Name Type 119 SCANEN 120 NC 121 X1 122 X2 123 VDDAP 124 GNDA Gnd 125 VDDAR 126 GNDA Gnd 127 GNDA Gnd 128 TEST2 Note Power supply Input ...
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KS8995MA Pin Description (by Name) Pin Number Pin Name Type 39 FXSD4 38 FXSD5 124 GNDA Gnd 42 GNDA Gnd 44 GNDA Gnd 2 GNDA Gnd 16 GNDA Gnd 30 GNDA Gnd 6 GNDA Gnd 12 GNDA Gnd 21 GNDA ...
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KS8995MA Pin Number Pin Name Type 97 LED3-1 Ipu/O 96 LED3-2 Ipu/O 95 LED4-0 Ipu/O 94 LED4-1 Ipu/O 93 LED4-2 Ipu/O 92 LED5-0 Ipu/O 91 LED5-1 Ipu/O 90 LED5-2 Ipu/O 107 MDC 108 MDIO 1 MDI-XDIS 45 MUX1 46 MUX2 ...
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KS8995MA Pin Number Pin Name Type 57 PMTXC 55 PMTXD0 54 PMTXD1 53 PMTXD2 52 PMTXD3 51 PMTXEN 56 PMTXER 114 PS0 113 PS1 47 PWRDN_N 48 RESERVE 115 RST_N 5 RXM1 11 RXM2 20 RXM3 26 RXM4 33 RXM5 ...
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KS8995MA Pin Number Pin Name Type 86 SCONF1 85 SCRS Ipd/O 78 SMRXC 83 SMRXD0 Ipd/O 82 SMRXD1 Ipd/O 81 SMRXD2 Ipd/O 80 SMRXD3 Ipd/O 79 SMRXDV Ipd/O 75 SMTXC 73 SMTXD0 72 SMTXD1 71 SMTXD2 70 SMTXD3 69 SMTXEN ...
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KS8995MA Pin Number Pin Name Type 110 SPIC/SCL 111 SPID/SDA 109 SPIQ 112 SPIS_N 128 TEST2 118 TESTEN 8 TXM1 14 TXM2 23 TXM3 29 TXM4 36 TXM5 7 TXP1 13 TXP2 22 TXP3 28 TXP4 35 TXP5 123 VDDAP ...
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KS8995MA Pin Number Pin Name Type 89 VDDC 117 VDDC 59 VDDIO 77 VDDIO 100 VDDIO 121 X1 122 X2 Note Power supply Input Output. M9999-051305 (1) Port Pin Function P 1.8V digital ...
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KS8995MA Pin Configuration 103 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2 1 May 2005 128-Pin PQFP (PQ) 21 Micrel, Inc. 65 ...
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KS8995MA Introduction The KS8995MA contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode five-port integrated switch. The ...
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KS8995MA detect, and FXSDx ‘L’ is below the 1.25V reference to indicate no signal. When FXSDx is below 0.6V then 100BASE-FX mode is disabled. Since there is no auto-negotiation for 100BASE-FX mode, ports 4 and 5 must be forced to ...
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KS8995MA Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995MA is guaranteed to learn 1K addresses and distinguishes itself from ...
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KS8995MA May 2005 Start -Search VLAN table. NO VLAN ID PTF1=NULL -Ingress VLAN filtering VALID? -Discard NPVID check YES Search complete. FOUND Search based on Search Static Get PTF1 from DA or DA+FID Table static table. NOT FOUND Search complete. ...
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KS8995MA Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet is dropped. Illegal Frames The KS8995MA discards frames of less than 64 bytes and can be programmed to accept frames up to 1536 ...
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KS8995MA SNI Signal MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC MDC MDIO PHY Mode Connection External KS8995MA MAC Signal MTXEN SMTXEN MTXER SMTXER MTXD3 SMTXD[3] MTXD2 SMTXD[2] MTXD1 SMTXD[1] MTXD0 SMTXD[0] ...
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KS8995MA The MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode. These interfaces are nibble-wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals ...
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KS8995MA Learning state: only packets to and from the processor are forwarded. Learning is enabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.” Software action: The processor should program the static MAC table with ...
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KS8995MA Tx Port Ingress Tag Field “Tag Insertion” (0x810+ port mask) (0x810+ port mask) (0x810+ port mask) (0x810+ port mask) Not tagged Don’t care Table 5. STPID Egress Rules (Processor to Switch Port 5) For packets from regular ports (port ...
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KS8995MA Port Mirroring Support KS8995MA supports “port mirror” comprehensively as: 1. “Receive Only” mirror on a port. All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “rx ...
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KS8995MA SA+FID found in Dynamic MAC table No Yes Advanced VLAN features are also supported in KS8995MA, such as “VLAN ingress filtering” and “discard non PVID” defined in Register 18 bit 6 and bit 5. These features can be controlled ...
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KS8995MA Configuration Interface The KS8995MA can function as a managed switch or unmanaged switch EEPROM or micro-controller exists, the KS8995MA will operate from its default setting. Some default settings are configured via strap in options as indicated in ...
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KS8995MA Pin # Pin Name PU/PD 86 SCONF1 Ipd 87 SCONF0 Ipd 90 LED5-2 Ipu/O 91 LED5-1 Ipu/O 113 PS1 Ipd 114 PS0 Ipd 128 TEST2 NC Note connect. Ipd = Input w/ internal pull-down. Ipu/O ...
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KS8995MA Master Serial Bus Configuration If a 2-wire EEPROM exists, the KS8995MA can perform more advanced features like broadcast storm protection and rate control. The EEPROM should have the entire valid configuration data from Register 0 to ...
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KS8995MA To use the KS8995MA SPI the board level, connect KS8995MA pins as follows: KS8995MA KS8995MA Pin Number Signal Name 112 SPIS_N 110 SPIC 111 SPID 109 SPIQ 2. Set the input signals PS[1:0] (pins 113 and 114, ...
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KS8995MA SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ READ COMMAND May 2005 WRITE ADDRESS Figure 8. ...
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KS8995MA SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ Byte 2 SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID SPIQ D7 ...
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KS8995MA Register Description Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F ...
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KS8995MA Address Name Register 2 (0x02): Global Control 0 7 Reserved 6-4 802.1p Base Priority 3 Enable PHY MII 2 Buffer Share Mode 1 UNH Mode 0 Link Change Age Register 3 (0x03): Global Control 1 7 Pass All Frames ...
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KS8995MA Address Name 2 Aging Enable 1 Fast age Enable 0 Aggressive Back Off Enable Register 4 (0x04): Global Control 2 7 Unicast Port-VLAN Mismatch Discard 6 Multicast Storm Protection Disable 5 Back Pressure Mode 4 Flow Control and Back ...
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KS8995MA Address Name 1 Legal Maximum Packet Size Check Disable 0 Priority Buffer Reserve Register 5 (0x05): Global Control 3 7 802.1q VLAN Enable 6 IGMP Snoop Enable on Switch MII Interface 5 Enable Direct Mode on Switch MII Interface ...
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KS8995MA Address Name 5 Switch MII Flow Control Enable 4 Switch MII 10BT 3 Null VID Replacement 2-0 Broadcast Storm Protection Rate Bit [10:8] Register 7 (0x07): Global Control 5 7-0 Broadcast Storm Protection Rate Bit [7:0] Note: 1. 148,800 ...
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KS8995MA Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register ...
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KS8995MA Address Name 5 Transmit Sniff 4-0 Port VLAN Membership Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Port 4 Control 2 Register 82 ...
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KS8995MA Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Port 4 Control 3 Register 83 (0x53): Port 5 Control 3 Address Name 7-0 Default ...
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KS8995MA Register 24 (0x18): Port 1 Control 8 Register 40 (0x28): Port 2 Control 8 Register 56 (0x38): Port 3 Control 8 Register 72 (0x48): Port 4 Control 8 Register 88 (0x58): Port 5 Control 8 Address Name 7-0 Receive ...
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KS8995MA Address Name 3 High Priority Receive Rate Flow Control Enable 2 Transmit Differential Priority Rate Control 1 Low Priority Transmit Rate Control Enable 0 High Priority Transmit Rate Control Enable Register 28 (0x1C): Port 1 Control 12 Register 44 ...
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KS8995MA Address Name 0 Advertised 10BT Half-Duplex Capability Note: Port Control 12 and 13, and Port Status 0 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition. Register 29 (0x1D): Port 1 Control 13 Register ...
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KS8995MA Register 31 (0x1F): Port 1 Control 14 Register 47 (0x2F): Port 2 Control 14 Register 63 (0x3F): Port 3 Control 14 Register 79 (0x4F): Port 4 Control 14 Register 95 (0x5F): Port 5 Control 14 Address Name 7 PHY ...
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KS8995MA Address Name Register 106 (0x6A): MAC Address Register 2 7-0 MACA[31:24] Register 107 (0x6B): MAC Address Register 3 7-0 MACA[23:16] Register 108 (0x6C): MAC Address Register 4 7-0 MACA[15:8] Register 109 (0X6D): MAC Address Register 5 7-0 MACA[7:0] Use ...
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KS8995MA Address Name Register 121 (0x79): Digital Testing Status 0 7-0 Factory Testing Register 122 (0x7A): Digital Testing Status 1 7-0 Factory Testing Register 123 (0x7B): Digital Testing Control 0 7-0 Factory Testing Register 124 (0x7C): Digital Testing Control 1 ...
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KS8995MA Static MAC Address KS8995MA has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table ...
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KS8995MA Examples: (1) Static Address Table Read (read the 2nd entry) Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (60-56) Read Register 114 (55-48) ...
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KS8995MA VLAN Address The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 =1), this table is used to retrieve VLAN information that is associated with the ingress packet. The information ...
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KS8995MA Dynamic MAC Address This table is read only. The contents are maintained by the KS8995MA only. Address Name Format of Dynamic MAC Address Table (1K entries) 68 MAC Empty 67- Valid Entries 57-56 Time Stamp 55 Data ...
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KS8995MA MIB Counters The MIB counters are provided on per port basis. The indirect memory is as below: For port 1 Offset Counter Name 0x0 RxLoPriorityByte 0x1 RxHiPriorityByte 0x2 RxUndersizePkt 0x3 RxFragments 0x4 RxOversize 0x5 RxJabbers 0x6 RxSymbolError 0x7 RxCRCerror ...
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KS8995MA For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f) For port 4, the base is 0x60, same offset definition (0x60-0x7f) For port 5, the base is ...
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KS8995MA (2) MIB counter read (read port counter) Write to Register 110 with 0x1c (read MIB counter selected) Write to Register 111 with 0x2e (trigger the read operation ) Then Read Register 117 (counter value 31-24) // ...
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KS8995MA MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” ...
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KS8995MA Address Name Register 1: MII Status 15 T4 Capable 14 100 Full Capable 13 100 Half Capable 12 10 Full Capable 11 10 Half Capable 10-7 Reserved 6 Preamble Suppressed 5 AN Complete 4 Far End Fault 3 AN ...
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KS8995MA Address Name Register 5: Link Partner Ability 15 Next Page 14 LP ACK 13 Remote Fault 12-11 Reserved 10 Pause 9 Reserved 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 Full 5 Adv 10 Half 4-0 ...
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KS8995MA Absolute Maximum Ratings Supply Voltage ( ............................. –0.5V to +2.4V DDAR, DDAP, DDC ( ........................................ –0.5V to +4.0V DDAT, DDIO Input Voltage ............................................... –0.5V to +4.0V Output Voltage ............................................ –0.5V to +4.0V Lead Temperature ...
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KS8995MA Symbol Parameter 100BASE-TX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of I SET SET Output Jitters 10BASE-TX Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer Peak Differential ...
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KS8995MA Timing Diagrams Receive Timing SCL SDA Figure 12. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 13. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time ...
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KS8995MA Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 M9999-051305 ts2 tcyc2 th2 Figure 14. SNI Input Timing tcyc2 ...
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KS8995MA Receive Timing MRXCLK MTXEN MTXER MTXD[3:0] Figure 16. MAC Mode MII Timing – Data Received from MII Transmit Timing MTXCLK MRXDV MRXD[3:0] Figure 17. MAC Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BASE-T) ...
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KS8995MA Receive Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 18. PHY Mode MII Timing – Data Received from MII Transmit Timing MRXCLK MRXDV MRXD[3:0] Figure 19. PHY Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BASE-T) ...
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KS8995MA SPIS_N tCHSL SPIC tDVCH SPID SPIQ Symbol Parameter f Clock Frequency C t SPIS_N Inactive Hold Time CHSL t SPIS_N Active Set-Up Time SLCH t SPIS_N Active Hold Time CHSH t SPIS_N Inactive Set-Up Time SHCH t SPIS_N Deselect ...
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KS8995MA SPIS_N SPIC tCLQX SPIQ SPID Symbol Parameter f Clock Frequency C t SPIQ Hold Time CLQX t Clock Low to SPIQ Valid CLQV t Clock High Time CH t Clock Low Time CL t SPIQ Rise Time QLQH t ...
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KS8995MA Supply Voltage RST_N Strap-In Value Strap-In / Output Pin Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC Reset Circuit Diagram ...
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KS8995MA Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio ...
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... KS8995MA Package Information MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. ...