HCPL-0710-500E Avago Technologies US Inc., HCPL-0710-500E Datasheet

OPTOCOUPLER CMOS 12MBD 8-SOIC

HCPL-0710-500E

Manufacturer Part Number
HCPL-0710-500E
Description
OPTOCOUPLER CMOS 12MBD 8-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of HCPL-0710-500E

Package / Case
8-SOIC (0.154", 3.90mm Width)
Voltage - Isolation
3750Vrms
Number Of Channels
1, Unidirectional
Current - Output / Channel
10mA
Data Rate
12.5MBd
Propagation Delay High - Low @ If
20ns
Input Type
Logic
Output Type
Push-Pull, Totem-Pole
Mounting Type
Surface Mount
Isolation Voltage
3750 Vrms
Maximum Continuous Output Current
10 mA
Maximum Fall Time
0.008 us
Maximum Forward Diode Current
10 mA
Output Device
Logic Gate Photo IC
Configuration
1 Channel
Maximum Baud Rate
12.5 MBd
Maximum Power Dissipation
150 mW
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
516-1489-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HCPL-0710-500E
Manufacturer:
AVAGO
Quantity:
30 000
Part Number:
HCPL-0710-500E
Manufacturer:
AVAGO/安华高
Quantity:
20 000
Part Number:
HCPL-0710-500E
0
DD2
O
2
**
HCPL-7710/0710
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Description
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-7710 or HCPL-0710 optocouplers
utilize the latest CMOS IC technology to achieve outstand-
ing performance with very low power consumption. The
HCPL-x710 require only two bypass capacitors for complete
CMOS compatibility.
Basic building blocks of the HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a CMOS detector IC. A
CMOS logic input signal controls the LED driver IC which
supplies current to the LED. The detector IC incorporates
an integrated photodiode, a high-speed transimped-
ance amplifier, and a voltage comparator with an output
driver.
Functional Diagram
**V
* Pin 3 is the anode of the internal LED and must be left
** A 0.1 µF bypass capacitor must be connected
GND
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
DD1
NC*
unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
between pins 1 and 4, and 5 and 8.
V
V
1
I
I
, INPUT
H
L
1
2
3
4
Lead (Pb) Free
RoHS 6 fully
compliant
(POSITIVE LOGIC)
TRUTH TABLE
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
LED1
LED1
OFF
ON
SHIELD
V
O
, OUTPUT
H
L
I
O
8
7
6
5
V
NC*
V
GND
DD2
O
2
**
V
I
, INPUT
H
L
(POSITIVE LOGIC)
TRUTH TABLE
Features
• +5 V CMOS compatibility
• 8 ns maximum pulse width distortion
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
• 10 kV/µs minimum common mode rejection
• -40°C to 100°C temperature range
• Safety and regulatory approvals
Applications
• Digital fieldbus isolation: DeviceNet, SDS, Profibus
• AC plasma display panel level shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
LED1
UL Recognized
3750 V rms for 1 min. per UL 1577
5000 V rms for 1 min. per UL 1577 (for HCPL-7710
option 020)
CSA Component Acceptance Notice #5
IEC/EN/DIN EN 60747-5-2
OFF
ON
– V
– V
IORM
IORM
V
O
= 630 Vpeak for HCPL-7710 Option 060
= 560 Vpeak for HCPL-0710 Option 060
, OUTPUT
H
L

Related parts for HCPL-0710-500E

HCPL-0710-500E Summary of contents

Page 1

... GND 2 • Microprocessor system interface Recognized 3750 V rms for 1 min. per UL 1577 5000 V rms for 1 min. per UL 1577 (for HCPL-7710 option 020) CSA Component Acceptance Notice #5 IEC/EN/DIN EN 60747-5-2 – 630 Vpeak for HCPL-7710 Option 060 IORM – 560 Vpeak for HCPL-0710 Option 060 ...

Page 2

... To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-7710-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/ DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: HCPL-0710 to order product of Small Outline SO-8 package in tube packaging and non RoHS compliant ...

Page 3

... TYPE NUMBER A XXXX YYWW 1.19 (0.047) MAX. 1.080 ± 0.320 (0.043 ± 0.013) Package Outline Drawing HCPL-7710 Package with Gull Wing Surface Mount Option 300 9.65 ± 0.25 (0.380 ± 0.010 1.19 (0.047) MAX. 1.080 ± 0.320 (0.043 ± 0.013) 2 ...

Page 4

... Package Outline Drawing HCPL-0710 Outline Drawing (Small Outline SO-8 Package XXXV 3.937 ± 0.127 YWW (0.155 ± 0.005 PIN ONE 0.406 ± 0.076 (0.016 ± 0.003) * 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 ± ...

Page 5

... T = 200 ° 150 °C smax smin Note: Non-halide flux should be used. Regulatory Information The HCPL-x710 have been approved by the following organizations: UL Recognized under UL 1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. Insulation and Safety Related Specifications ...

Page 6

... Solder Reflow Temperature Profile Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltages Logic High Input Voltage Logic Low Input Voltage Input Signal Rise and Fall Times 6 HCPL-7710 HCPL-0710 Symbol Option 060 Option 060 I-IV I-IV I-IV I-III I-III 55/100/21 55/100/21 ...

Page 7

Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are +25° Specifications Parameter Logic Low Input Supply Current [1] Logic High Input Supply Current ...

Page 8

... Mimimum Pulse Width is the shortest pulse width at which 10% maximum, Pulse Width Distortion can be guaranteed. Maximum Data Rate is the inverse of Minimum Pulse Width. Operating the HCPL-x710 at data rates above 12.5 MBd is possible provided PWD and data dependent jitter increases and relaxed noise margins are tolerable within the application. For instance, if the maximum allowable variation of bit width is 30%, the maximum data rate becomes 37 ...

Page 9

... Figure 11. Thermal derating curve, dependence of Safety Limiting Value with case temperature per IEC/EN/DIN EN 60747-5- (C) A Figure 6. Typical fall time vs. temperature. HCPL-0710 fig (pF) I Figure 9. Typical rise time vs. load capacitance. HCPL-0710 fig 9 SURFACE MOUNT SO8 PRODUCT 800 P (mW) S 700 I (mA) S 600 500 400 300 200 (150) 100 100 125 150 175 200 CASE TEMPERATURE - C A ...

Page 10

... Application Information Bypassing and PC Board Layout The HCPL-x710 optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL-x710 use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 12, the only external components V 1 DD1 ...

Page 11

... PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order 30% of the minimum pulse width is tolerable. The PWD specification for the HCPL-x710 (10%) maximum across recommend- ed operating conditions. 10% maximum is dictated by the most stringent of the three fieldbus standards, PROFIBUS. ...

Page 12

... Isolation of nodes connected to any of the three types of digital field bus networks is best achieved by using the HCPL-x710 optocouplers. For each network, the HCPL- x710 satisify the critical propagation delay and pulse width distortion requirements over the temperature range of 0°C to +85°C, and power supply voltage range of 4 ...

Page 13

... POWER NETWORK POWER SUPPLY Figure 18. Typical DeviceNet node. Implementing DeviceNet and SDS with the HCPL-x710 HCPL-0710 fig 17 With transmission rates Mbit/s, both DeviceNet and SDS are based upon the same broadcast-oriented, communications protocol — the Controller Area Network (CAN). Three types of isolated nodes are rec- ...

Page 14

... HCPL-x710 ensure the network will not “lock-up” if either AC line power to the node is lost or the node powered-off. Specifically, when input power (V the HCPL-x710 located in the transmit path is eliminat- ed, a RECESSIVE bus state is ensured as the HCPL-x710 output voltage ( HIGH. O NODE/APP SPECIFIC ...

Page 15

... HCPL-x710 ensure the network will not “lock-up” if either AC line power to the node is lost or the node powered-off. Specifically, when input power (V the HCPL-x710 located in the transmit path is eliminat- ed, a RECESSIVE bus state is ensured as the HCPL-x710 output voltage (V AC LINE 5 V REG. ...

Page 16

... Power Supplies and Bypassing The recommended DeviceNet application circuit is shown in Figure 22. Since the HCPL-x710 are fully com- patible with CMOS logic level signals, the optocoupler is connected directly to the CAN transceiver. Two bypass capacitors (with values between 0.01 and 0.1 µF) are ...

Page 17

... Power Supplies and Bypassing The recommended PROFIBUS application circuit is shown in Figure 24. Since the HCPL-x710 are fully com- patible with CMOS logic level signals, the ler is connected directly to the transceiver. Two bypass capacitors (with values between 0.01 and 0.1 µF) are required and should be located as close as possible to the input and output power-supply pins of the HCPL- x710 ...

Page 18

For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © ...

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