HCPL-260L-020 Avago Technologies US Inc., HCPL-260L-020 Datasheet - Page 20

• Manufacturer Part Number: HCPL-260L-020
• Description: OPTOCOUPLER 15MBD 3.3V UL 8-DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-260L-020

• Package / Case: 8-DIP (0.300", 7.62mm)
• Voltage - Isolation: 5000Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 50mA
• Data Rate: 15MBd
• Propagation Delay High - Low @ If: 50ns @ 7.5mA
• Current - Dc Forward (if): 20mA
• Input Type: DC
• Output Type: Open Collector
• Mounting Type: Through Hole
• Isolation Voltage: 3750 Vrms
• Maximum Continuous Output Current: 50 mA
• Maximum Fall Time: 20 ns
• Maximum Forward Diode Current: 20 mA
• Maximum Rise Time: 45 ns
• Minimum Forward Diode Voltage: 1.4 V
• Output Device: Logic Gate Photo IC
• Configuration: 1 Channel
• Maximum Baud Rate: 15 MBps
• Maximum Forward Diode Voltage: 1.75 V
• Maximum Reverse Diode Voltage: 5 V
• Maximum Power Dissipation: 85 mW
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Likewise for common-mode transients which occur
when the LED is off (i.e. CMR
if an imbalance between I
I
optocoupler, the transient “signal” may cause the output
to spike below 2 V (which consti tutes a CMR
By using the recommended circuit in Figure 13, good
CMR can be achieved. The balanced I
help equalize I
I
and C
CMR with Other Drive Circuits
CMR performance with drive circuits other than that
shown in Figure 13 may be enhanced by following these
guidelines:
1. Use of drive circuits where current is shunted from the
2. Use of I
Figure 15 shows a circuit which can be used with any
totem-pole-output TTL/LSTTL/HCMOS logic gate. The
buffer PNP transistor allows the circuit to be used with
logic devices which have low current-sinking capability.
It also helps maintain the driving-gate power-supply cur-
rent at a constant level to minimize ground shifting for
other devices connected to the input-supply ground.
When using an open-collector TTL or open-drain CMOS
logic gate, the circuit in Figure 16 may be used. When
using a CMOS gate to drive the optocoupler, the circuit
shown in Figure 17 may be used. The diode in parallel
with the R
LED.
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0581EN
AV02-0616EN - February 8, 2010
F
LED
equal to or greater than the switching threshold of the
LED in the LED “off” state (as shown in Figures 15 and
16). This is beneficial for good CMR
is modulated from transient coupling through C
LC
.
FH
LED
> 3.5 mA. This is good for high CMR
LP
speeds the turn-off of the optocoupler
and I
LN
to reduce the amount by which
LP
H
and I
, since the output is “high”),
LN
results in a transient
LED
H
.
-setting resistors
H
failure).
L
.
www.avagotech.com
LA
TTL/CMOS
Figure 15. TTL interface circuit.
OPEN-COLLECTOR/
Figure 16. TTL open-collector/open drain gate drive circuit.
OUTPUT LOGIC
Figure 17. CMOS gate drive circuit.
TOTEM-POLE
74L504
GATE)
(ANY
LOGIC GATE)
(OR ANY
OPEN-DRAIN
74HC04
GATE)
(OR ANY
V
74HC00
CC
V
CC
V
CC
2N3906
(ANY PNP)
1N4148
220 Ω
420 Ω
(MAX)
1
2
3
4
R
HCPL-260L
1
2
3
4
HCPL-260L
LED
1
2
3
4
HCPL-260L
LED
LED