HCPL-263N#300 Avago Technologies US Inc., HCPL-263N#300 Datasheet - Page 10

• Manufacturer Part Number: HCPL-263N#300
• Description: OPTOCOUPLER 2CH 10MBD 8-SMD GW
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-263N#300

• Package / Case: 8-SMD Gull Wing
• Voltage - Isolation: 3750Vrms
• Number Of Channels: 2, Unidirectional
• Current - Output / Channel: 50mA
• Data Rate: 10MBd
• Propagation Delay High - Low @ If: 53ns @ 3.5mA
• Current - Dc Forward (if): 10mA
• Input Type: DC
• Output Type: Open Collector
• Mounting Type: Surface Mount, Gull Wing
• Isolation Voltage: 3750 Vrms
• Maximum Continuous Output Current: 50 mA
• Maximum Fall Time: 12 ns
• Maximum Forward Diode Current: 10 mA
• Maximum Rise Time: 42 ns
• Minimum Forward Diode Voltage: 1 V
• Output Device: Logic Gate Photo IC
• Configuration: 2 Channel
• Maximum Baud Rate: 10 MBps
• Maximum Forward Diode Voltage: 1.6 V
• Maximum Reverse Diode Voltage: 3 V
• Maximum Power Dissipation: 60 mW
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Package Characteristics
All Typicals at T
*Ratings apply to all devices except otherwise noted in the Package column.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equip-
ment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage. ”
†For 8-pin DIP package devices (HCPL-261A/261N/263A/263N) only.
Notes:
10. The t
11. Propagation delay skew (t
12. Single channel products only (HCPL-261A/261N/061A/061N).
13. Common mode transient immunity in a Logic High level is the maximum tolerable |dV
14. Common mode transient immunity in a Logic Low level is the maximum tolerable |dV
15. For sinusoidal voltages
16. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as shown in Figure 19. Total
17. Pulse Width Distortion (PWD) is defined as the difference between t
18. No external pull up is required for a high logic state on the enable input of a single channel product. If the V
19. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel parts only.
10
1. Peaking circuits may be used which produce transient input currents up to 30 mA, 50 ns maximum pulse width, provided the average current
2. 1 minute maximum.
3. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
4. Each channel.
5. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
6. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V
8. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together.
9. The t
(Input-Input)
Parameter
Input-Output
Momentary With-
stand Voltage**
Input-Output
Resistance
Input-Output
Capacitance
Input-Input
Insulation
Leakage Current
Resistance
(Input-Input)
Capacitance
does not exceed 10 mA.
tion current limit, I
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
tion current limit, I
the output pulse.
the output pulse.
test conditions and operating temperature.
the output will remain in a Logic High state (i.e., Vo > 2.0 V).
the output will remain in a Logic Low state (i.e., V
(|dV
lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
will result in improved CMR performance.
CM
PLH
PHL
/dt|)max = πf
propagation delay is measured from the 1.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of
propagation delay is measured from the 1.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of
A
= 25°C
I-O
I-O
CM
≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in the
≤ 5 µA).
V
CM(P-P)
Sym.
V
R
C
PSK
R
C
I
ISO
I-O
I-O
I-I
.
I-I
I-I
) is equal to the worst case difference in t
Dual 8-pin DIP
Dual Channel
Dual Channel
OPT 020†
Dual SO-8
Package*
O
< 0.8 V).
5000
3750
Min.
0.005
0.03
0.25
Typ.
10
10
0.6
PLH
12
11
PLH
and t
and/or t
PHL
Max.
for any given device.
PHL
that will be seen between any two units under the same
CM
V rms
CM
Units
/dt| of the common mode pulse, V
µA
pF
pF
/dt| of the common mode pulse, V
Ω
Ω
RH ≤ 50%,
t = 1 min.,
T
V
f = 1 MHz,
T
RH ≤ 45%,
t = 5 s,
V
f = 1 MHz
Test Conditions
A
A
I-I
I-O
= 25°C
= 25°C
= 500 V
= 500 Vdc
E
RMS
RMS
pin is not used, tying V
for 1 second (leakage detec-
for 1 second (leakage detec-
CM
CM
, to assure that
, to assure that
Fig.
E
to V
Note
5, 7
5, 6
4, 8
4, 8
19
19
19
CC