DS1982-F3+ Maxim Integrated Products, DS1982-F3+ Datasheet
DS1982-F3+
Specifications of DS1982-F3+
Related parts for DS1982-F3+
DS1982-F3+ Summary of contents
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... DS1982 communications requirements to reader Reads over a wide voltage range of 2.8V to 6.0V from -40°C to +85°C; programs at 11.5V to 12.0V from -40°C to +50°C ORDERING INFORMATION DS1982-F3+ F3 MicroCan DS1982-F5+ F5 MicroCan +Denotes a lead(Pb)-free/RoHS-compliant product. EXAMPLES OF ACCESSORIES DS9096P ...
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... DS1982 become accessible and the bus master may issue any one of the five memory function commands specific to the DS1982 to read or program the various data fields. The protocol for these memory function commands is described in Figure 6. All data is read and written least significant bit first. ...
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... LASERED ROM Each DS1982 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (see Figure 3). The 64-bit ROM and ROM Function Control section allow the DS1982 to operate as a 1-Wire device and follow the 1-Wire protocol detailed in the section “ ...
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... DS1982 BLOCK DIAGRAM Figure 1 Page DS1982 ...
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... SEARCH ROM SKIP ROM WRITE MEMORY WRITE STATUS BYTE READ MEMORY READ STATUS BYTE READ DATA/GENERATE 8-BIT CRC 48- Bit Serial Number LSB MSB Page DS1982 OTHER DEVICES DATA FIELD AFFECTED: 64-BIT ROM 64-BIT ROM 64-BIT ROM N/A 1024-BIT EPROM EPROM STATUS BYTES ...
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... EPROM The memory map in Figure 5 shows the 1024-bit EPROM section of the DS1982 that is configured as four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit CRC from the DS1982 that confirms proper receipt of the data ...
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... To execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. All bits transferred to the DS1982 and received back by the bus master are sent least significant bit first. ...
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... MEMORY FUNCTION FLOW CHART Figure 6 Page DS1982 ...
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... MEMORY FUNCTION FLOW CHART (cont’d) Figure 6 Page DS1982 ...
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... MEMORY FUNCTION FLOW CHART (cont’d) Figure 6 Page DS1982 ...
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... Read Status command supplies an 8-bit CRC that is based on and always is consistent with the current data stored in the EPROM Status data field. After the 8-bit CRC is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is issued. The Read Status command sequence can be exited at any point by issuing a Reset Pulse. ...
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... EPROM data field. After the 8-bit CRC of the last page is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is issued. The Read Data/Generate 8-Bit CRC command sequence can be exited at any point by issuing a Reset Pulse ...
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... The bus master will issue the next byte of data using eight write time slots. As the DS1982 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address, and the result is an 8-bit CRC of the new data byte and the LSB of the new address ...
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... For both of these cases, the decision to continue (to apply a program pulse to the DS1982) is made entirely by the bus master, since the DS1982 will not be able to determine if the 8-bit CRC calculated by the bus master agrees with the 8-bit CRC calculated by the DS1982 incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS1982 ...
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... Reset Pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1982 is on the bus and is ready to operate. For more details, see the “1-Wire Signaling” section. ...
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... DS1982 EQUIVALENT CIRCUIT Figure 7 BUS MASTER CIRCUIT Figure 8 Page DS1982 ...
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... ROM FUNCTIONS FLOW CHART Figure 9 Page DS1982 ...
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... DS1982. During write time slots, the delay circuit determines when the DS1982 will sample the data line. For a read data time slot transmitted, the delay circuit determines how long the DS1982 will hold the data line low overriding the 1 generated by the master. If ...
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... CRC GENERATION The DS1982 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1982 to determine if the ROM data has been received error-free by the bus master. The equivalent ...
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... READ/WRITE TIMING DIAGRAM Figure 11 Write-1 Time Slot Write-0 Time Slot RESISTOR MASTER DS1982 60 s t < 120 s SLOT 1 s t < 15 s LOW1 1 s t < REC 60 s t < 120 s < t LOW0 SLOT 1 s t < REC Page DS1982 ...
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... Read-data Time Slot RESISTOR MASTER DS1982 PROGRAM PULSE TIMING DIAGRAM Figure 12 60 s t < 120 s SLOT 1 s t < 15 s LOWR 0 t < 45 s RELEASE 1 s t < REC = 15 s t RDV < 1 Page DS1982 ...
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... LOW0 t exactly 15 RDV RELEASE REC t 480 RSTH t 480 RSTL t 15 PDHIGH t 60 PDLOW 480 0.5 FP Page DS1982 MAX UNITS NOTES + 12 25C) A MAX UNITS NOTES 800 pF 9 MAX UNITS NOTES 120 s s 15 s 120 s 45 s ...
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... The accumulative duration of the programming pulses for each address must not exceed 5 ms. and a maximum time slot of 120 after power has been applied the parasite capacitance will not affect may have to be reduced to as much as 0.5V to always ILMAX Page DS1982 ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time © 2009 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc. DS1982 PAGES CHANGED 1 1 ...