MT4LSDT864HY-133G2 Micron Technology Inc, MT4LSDT864HY-133G2 Datasheet

MODULE SDRAM 64MB 144-SODIMM

MT4LSDT864HY-133G2

Manufacturer Part Number
MT4LSDT864HY-133G2
Description
MODULE SDRAM 64MB 144-SODIMM
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT4LSDT864HY-133G2

Memory Type
SDRAM
Memory Size
64MB
Speed
133MHz
Package / Case
144-SODIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SMALL-OUTLINE
SDRAM MODULE
Features
• PC100 and PC133 compliant 144-pin, small-outline,
• Utilizes 125 MHz and 133 MHz SDRAM
• Unbuffered
• 32MB (4Meg x 64), 64MB (8 Meg x 64), and 128MB
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode: Standard and Low Power
• 32MB and 64MB: 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
Table 1:
CL = CAS (READ) latency
Table 2:
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
MARKING
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
MODULE
dual in-line memory module (SODIMM)
components
(16 Meg x 64)
edge of system clock
be changed every clock cycle
(15.625µs refresh interval); 128MB: 64ms, 8,192-
cycle refresh (7.81µs refresh interval)
-13E
-133
-10E
FREQUENCY
133 MHz
133 MHz
100 MHz
CLOCK
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
Timing Parameters
Address Table
CL = 2
ACCESS TIME
5.4ns
6ns2
CL = 3
5.4ns
64Mb (4 Meg x16)
4 (BA0, BA1)
4K (A0–A11)
256 (A0–A7)
SETUP
TIME
1.5ns
1.5ns
1 (S0#)
32MB
2ns
4K
HOLD
TIME
0.8ns
0.8ns
1ns
1
MT4LSDT464(L)H(I) – 32MB
MT4LSDT864(L)H(I) – 64MB
MT4LSDT1664(L)H(I) – 128MB
For the latest data sheet, please refer to the Micron
site:
Standard 1.00in. (25.40 mm)
Options
• Self Refresh Current
• Operating Temperature Range
• Package
• Memory Clock/CAS Latency
NOTE:
Figure 1: 144-Pin SODIMM (MO-190)
128Mb (8 Meg x 16)
Standard
Low-Power
Commercial (0°C to + 65°C
Industrial (-40°C to +85°C)
144-pin SODIMM (standard)
144-pin SODIMM (lead-free)
7.5ns (133 MHz)/CL = 2
7.5ns (133 MHz)/CL = 3
10ns (100 MHz)/CL = 2
32MB, 64MB, 128MB (x64, SR)
www.micron.com/products/modules
4 (BA0, BA1)
4K (A0–A11)
512 (A0–A8)
1. Contact Micron for product availability.
2. Low Power and Industrial Temperature options
1 (S0#)
64MB
4K
not available concurrently; Industrial Tempera-
ture option available in -133 speed only.
144-PIN SDRAM SODIMM
©2004 Micron Technology, Inc. All rights reserved.
)
256Mb (16 Meg x 16)
4 (BA0, BA1)
8K (A0–A12)
512 (A0–A8)
128MB
1 (S0#)
8K
Marking
None
None
-13E
-10E
L
-133
I
1, 2
Y
1, 2
G
1
®
Web

Related parts for MT4LSDT864HY-133G2

MT4LSDT864HY-133G2 Summary of contents

Page 1

... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 32MB, 64MB, 128MB (x64, SR) MT4LSDT464(L)H(I) – 32MB MT4LSDT864(L)H(I) – 64MB MT4LSDT1664(L)H(I) – 128MB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 144-Pin SODIMM (MO-190) Standard 1.00in. (25.40 mm) Options • Self Refresh Current Standard Low-Power • ...

Page 2

Part Numbers PART NUMBER MT4LSDT464(L)HG-13E_ MT4LSDT464(L)HY-13E_ MT4LSDT464(L)H(I)G-133_ MT4LSDT464(L)H(I)Y-133_ MT4LSDT464(L)HG-10E_ MT4LSDT464(L)HY-10E_ MT4LSDT864(L)HG-13E_ MT4LSDT864(L)HY-13E_ MT4LSDT864(L)H(I)G-133_ MT4LSDT864(L)H(I)Y-133_ MT4LSDT864(L)HG-10E_ MT4LSDT864(L)HY-10E_ MT4LSDT1664(L)HG-13E_ MT4LSDT1664(L)HY-13E_ MT4LSDT1664(L)H(I)G-133_ MT4LSDT1664(L)H(I)Y-133_ MT4LSDT1664(L)HG-10E_ MT4LSDT1664(L)HY-10E_ NOTE: 1. The designators for component and PCB revision are the last two characters of each part number. ...

Page 3

... S0# 105 DNU 107 SS NOTE: 1. Pin Connect for 32MB and 64MB modules, or A12 for 128MB modules. Figure 2: 144-Pin SODIMM Pin Locations Front View U1 PIN 1 (all odd pins) 09005aef80748a77 SD4C4_8_16X64HG.fm - Rev. C 6/04 EN 32MB, 64MB, 128MB (x64, SR) Table 4: PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL ...

Page 4

Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 more information PIN NUMBERS 65, 66, 67 RAS#, CAS#, WE 23, 24, 25, 26, 115, 116, 117, DQMB0–DQMB7 ...

Page 5

... Not Connected: These pins should be left unconnected. DNU – Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. 5 144-PIN SDRAM SODIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 6

... A0-A12 (128MB) BA0-BA1 NOTE: 1. All resistor values are 10 unless otherwise specified. 2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at: www.micron.com/support/numbering.html. 09005aef80748a77 SD4C4_8_16X64HG.fm - Rev. C 6/04 EN 32MB, 64MB, 128MB (x64, SR) Figure 3: Functional Block Diagram DQMB4 ...

Page 7

... These modules use internally configured quad-bank SDRAMs with a synchronous interface (all signals are registered on the positive edge of the clock signal CK). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...

Page 8

Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst (sequential or inter- leaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 ...

Page 9

Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES WITHIN LENGTH ADDRESS TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1-2 8 ...

Page 10

Reserved states should not be used, because un- known operation or incompatibility with future ver- sions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 ...

Page 11

Commands The Truth Table provides a quick reference of avail- able commands. This is followed by written descrip- tion of each command. For a more detailed des- Table 8: Truth Table – SDRAM Commands and DQMB Operation CKE is HIGH ...

Page 12

Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...

Page 13

Table 11: I Specifications and Conditions – 64MB DD Notes 11, 13; notes appear on page 16; V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst = 2; READ WRITE (MIN) STANDBY CURRENT: ...

Page 14

Table 13: Capacitance Notes: 1; notes appear on page 16 PARAMETER Input Capacitance: Address and Command, CKE, DQMB Input Capacitance: CK Input/Output Capacitance: DQ Table 14: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 32; ...

Page 15

Table 15: AC Functional Characteristics Notes 11, 32; notes appear on page 16 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup ...

Page 16

Notes 1. All voltages referenced This parameter is sampled MHz 25°C; pin under test biased at A 1.4V dependent on output loading and cycle DD rates. Specified ...

Page 17

SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Fig- ure 6, Data Validity, and Figure 7, Definition ...

Page 18

Table 16: EEPROM Device Select Code Most significant bit (b7) is sent first Memory Area Select Code (two arrays) Protection Register Select Code Table 17: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential Read Byte ...

Page 19

Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...

Page 20

Table 20: Serial Presence-Detect Matrix “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”; notes appear at end of Serial Presence-Detect Matrix BYTE DESCRIPTION 0 Number of Bytes Used by Micron 1 Total Number of SPD Memory Bytes 2 Memory Type ...

Page 21

... Week of Manufacture in BCD 95-98 Module Serial Number 99-125 Manufacturer-specific Data (RSVD) 126 System Frequency 127 SDRAM Component & Clock Detail NOTE The value of RAS used for -13E modules is calculated from 09005aef80748a77 SD4C4_8_16X64HG.fm - Rev. C 6/04 EN 32MB, 64MB, 128MB (x64, SR) ENTRY (VERSION) t 45ns (-13E) ...

Page 22

Figure 10: 144-Pin SODIMM Dimensions 0.079 (2.00) R (2X) 0.071 (1.80) (2X) 0.236 (6.00) 0.100 (2.55) PIN 1 0.079 (2.00) 83.82 (3.30) PIN 144 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Released (No Mark): This data sheet ...

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