MT18VDDF12872G-335D3

Manufacturer Part NumberMT18VDDF12872G-335D3
DescriptionMODULE DDR SDRAM 1GB 184-DIMM
ManufacturerMicron Technology Inc
MT18VDDF12872G-335D3 datasheet
 


Specifications of MT18VDDF12872G-335D3

Memory TypeDDR SDRAMMemory Size1GB
Speed167MHzPackage / Case184-DIMM
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names557-1113
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DDR SDRAM
REGISTERED DIMM
Features
• 184-pin, dual in-line memory module (DIMM)
• Fast data transfer rates: PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR
SDRAM components
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Supports ECC error detection and correction
• 512MB (64 Meg x 72) and 1GB (128 Meg x 72)
• V
= V
Q = +2.5V
DD
DD
• V
= +2.3V to +3.6V
DDSPD
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
Table 1:
Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
512MB, 1GB (x72, ECC, SR)
184-PIN DDR SDRAM RDIMM
MT18VDDF6472 – 512MB
MT18VDDF12872 – 1GB
For the latest data sheet, please refer to the Micron
site:
www.micron.com/products/modules
Figure 1: 184-Pin DIMM (MO-206)
Standard PCB 1.125in. (28.58mm)
Alternate PCB
1.125in. (28.58mm)
Very Low Profile 0.72in. (18.29mm)
OPTIONS
• Operating Temperature Range
Commercial (0°C T
+70°C)
A
• Package
184-pin DIMM (standard)
1
184-pin DIMM (lead-free)
• Memory Clock, Speed, CAS Latency
6ns (166MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
10ns (100 MHz), 200 MT/s, CL = 2
• PCB
Low-Profile 1.125in. (28.58mm)
Very Low Profile 0.72in. (18.29mm)
NOTE:
1. Contact Micron for availability of products.
2. CL = CAS latency. Registered Mode will add one
clock cycle to CL.
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (64 Meg x 4)
512Mb (128 Meg x 4)
2K (A0–A9, A11)
4K (A0–A9, A11, A12)
1 (S0#)
1
©2004 Micron Technology, Inc. All rights reserved.
Web
MARKING
none
G
Y
2
-335
1
-262
1
-26A
-265
1
-202
See page 2
note
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
1 (S0#)

MT18VDDF12872G-335D3 Summary of contents

  • Page 1

    ... ECC, SR) 184-PIN DDR SDRAM RDIMM MT18VDDF6472 – 512MB MT18VDDF12872 – 1GB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 184-Pin DIMM (MO-206) Standard PCB 1.125in. (28.58mm) Alternate PCB 1.125in. (28.58mm) Very Low Profile 0.72in. (18.29mm) OPTIONS • ...

  • Page 2

    ... MT18VDDF12872G-335__ MT18VDDF12872Y-335__ MT18VDDF12872G-262__ MT18VDDF12872Y-262__ MT18VDDF12872G-26A__ MT18VDDF12872Y-26A__ MT18VDDF12872G-265__ MT18VDDF12872Y-265__ MT18VDDF12872G-202__ MT18VDDF12872Y-202__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDF6472G-265B1. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN CONFIGURATION ...

  • Page 3

    Table 3: Pin Assignment (184-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...

  • Page 4

    Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information. PIN NUMBERS SYMBOL 10 RESET# 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21 157 52, ...

  • Page 5

    Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information. PIN NUMBERS SYMBOL 12,13, 19, 20, DQ0–DQ63 23, 24, 28, 31, 33, 35, 39, ...

  • Page 6

    ... V DD SA0 SA1 SA2 RESET# Standard modules use the following DDR SDRAM devices: MT46V64M4FG (512MB); MT46V128M4FG (1GB) Lead-free modules use the following DDR SDRAM devices: MT46V64M4BG (512MB); MT46V128M4BG (1GB) 6 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM U22 U20 U15 U14 ...

  • Page 7

    ... U12 SA0 SA1 SA2 RESET# Standard modules use the following DDR SDRAM devices: MT46V64M4FG (512MB); MT46V128M4FG (1GB) Lead-free modules use the following DDR SDRAM devices: MT46V64M4BG (512MB); MT46V128M4BG (1GB) 7 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM DQS CS U24 DQS CS U23 ...

  • Page 8

    ... SA1 SA2 Standard modules use the following DDR SDRAM devices MT46V64M4FG (512MB); MT46V128M4FG (1GB) Lead-free modules use the following DDR SDRAM devices: MT46V64M4BG (512MB); MT46V128M4BG (1GB) Micron Technology, Inc., reserves the right to change products or specifications without notice. 8 512MB, 1GB (x72, ECC, SR) ...

  • Page 9

    ... DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...

  • Page 10

    Vio- lating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential or inter- leaved), A4–A6 specify the CAS latency, ...

  • Page 11

    Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...

  • Page 12

    DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operat- ing mode. All other combinations of values for A7–A12 are reserved for future use and/or test modes. Test modes and reserved states should ...

  • Page 13

    Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...

  • Page 14

    Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...

  • Page 15

    Table 12: IDD Specifications and Conditions – 512MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...

  • Page 16

    Table 13: IDD Specifications and Conditions – 1GB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...

  • Page 17

    Table 14: Capacitance Note: 11; notes appear on pages 21–24 PARAMETER Input/Output Capacitance: DQ, DQS Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) ...

  • Page 18

    Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1–5, 12-15, 29, 49; notes appear on pages 21–24; 0°C AC CHARACTERISTICS PARAMETER DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE ...

  • Page 19

    Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) Notes: 1–5, 12-15, 29, 49; notes appear on pages 21–24; 0°C AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level ...

  • Page 20

    Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued) Notes: 1–5, 12-15, 29, 49; notes appear on pages 21–24; 0°C AC CHARACTERISTICS PARAMETER REFRESH to REFRESH command interval Average periodic refresh interval Terminating ...

  • Page 21

    Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...

  • Page 22

    DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 ...

  • Page 23

    Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9V, which- ever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either - ...

  • Page 24

    I 2N specifies the DQ, DQS, and driven to a valid high or low logic level. I similar except address and control inputs to remain stable. Although I 2 ...

  • Page 25

    Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...

  • Page 26

    Table 17: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 PARAMETER SYMBOL Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle to Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter Half-Period Jitter t Input Clock Slew ...

  • Page 27

    Table 18: Register Timing Requirements and Switching Characteristics Note: 1 REGISTER SYMBOL PARAMERTER f Clock Frequency clock t Clock to Output Time pd t Reset to Output Time PHL t Pulse Duration w SSTL (bit pattern t Differential Inputs Active ...

  • Page 28

    ... NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules ...

  • Page 29

    SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 14, Data Validity, and Figure ...

  • Page 30

    Table 19: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 20: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read ...

  • Page 31

    Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...

  • Page 32

    Table 23: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 34 BYTE DESCRIPTION 0 Number of SPD Bytes Used By Micron 1 Total Number of Bytes In SPD Device 2 Fundamental Memory Type ...

  • Page 33

    Table 23: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 34 BYTE DESCRIPTION 30 Minimum RAS# Pulse Width, 31 Module Rank Density 32 Address and Command Setup Time Address and Command ...

  • Page 34

    ... The value of RAS used for -26A/-265 modules is calculated from 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met ...

  • Page 35

    Figure 18: 184-Pin DIMM Dimensions – Low-Profile PCB 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) 0.091 (2.30) TYP. U12 U13 PIN 184 Figure 19: 184-Pin DIMM Dimensions – Alternate Low-Profile ...

  • Page 36

    Figure 20: 184-Pin DIMM Dimensions – Very Low-Profile PCB 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2.55 (64.77) TYP. U12 U13 U14 PIN 184 NOTE: All ...