MT8VDDT6464HDG-40BF2 Micron Technology Inc, MT8VDDT6464HDG-40BF2 Datasheet

MODULE DDR 512MB 200-SODIMM

MT8VDDT6464HDG-40BF2

Manufacturer Part Number
MT8VDDT6464HDG-40BF2
Description
MODULE DDR 512MB 200-SODIMM
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT8VDDT6464HDG-40BF2

Memory Type
DDR SDRAM
Memory Size
512MB
Speed
400MT/s
Package / Case
200-SODIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
DDR SDRAM SMALL-
OUTLINE DIMM
Features
• 200-pin, small-outline, dual in-line memory
• Fast data transfer rates: PC3200
• Utilizes 400 MT/s DDR SDRAM components
• 256MB (32 Meg x 64) or 512MB (64 Meg x 64)
• V
• V
• 2.6V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
• Internal, pipelined double data rate (DDR)
• Bidirectional data strobe (DQS) transmitted/received
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
• Gold edge contacts
Table 1:
pdf: 09005aef80b575ca, source: 09005aef806e1d28
DDA8C32_64x64HDG.fm - Rev. D 9/04 EN
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
module (SODIMM)
aligned with data for WRITEs
architecture; two data accesses per clock cycle
with data—i.e., source-synchronous data capture
interval
DD
DDSPD
= V
DD
= +2.3V to +3.6V
Q = +2.6V
Address Table
256Mb (16 Meg x 16)
1
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
2 (S0#, S1#)
NOTE:
OPTIONS
• Package
• Memory Clock, Speed, CAS Latency
• PCB
256MB, 512MB (x64, DR) PC3200
MT8VDDT3264HD – 256MB
MT8VDDT6464HD – 512MB
For the latest data sheet, please refer to the Micron
site:
1.25in. (31.75mm)
256MB
Figure 1: 200-Pin SODIMM (MO-224)
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)
5ns (200 MHz), 400 MT/s, CL= 3
Standard 1.25in. (31.75mm)
8K
www.micron.com/products/modules
1. Consult Micron for product availability.
2. CL = CAS (READ) Latency.
200-PIN DDR SODIMM
512Mb (32 Meg x 16)
1
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
2 (S0#, S1#)
512MB
8K
2
©2004 Micron Technology, Inc.
MARKING
-40B
G
Y
Web

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MT8VDDT6464HDG-40BF2 Summary of contents

Page 1

... DDA8C32_64x64HDG.fm - Rev. D 9/04 EN 256MB, 512MB (x64, DR) PC3200 200-PIN DDR SODIMM MT8VDDT3264HD – 256MB MT8VDDT6464HD – 512MB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 200-Pin SODIMM (MO-224) 1.25in. (31.75mm) OPTIONS • Package 200-pin SODIMM (standard) 200-pin SODIMM (lead-free) • ...

Page 2

... Part Numbers and Timing Parameters PART NUMBER MODULE DENSITY 256MB MT8VDDT3264HDG-40B__ 256MB MT8VDDT3264HDY-40B__ MT8VDDT6464HDG-40B__ 512MB MT8VDDT6464HDY-40B__ 512MB NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3264HDG-40BA1. pdf: 09005aef80b575ca, source: 09005aef806e1d28 DDA8C32_64x64HDG ...

Page 3

Table 3: Pin Assignment (200-Pin SODIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 101 REF DQ19 103 SS 5 DQ0 55 DQ24 105 7 DQ1 57 V 107 DD 9 ...

Page 4

Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on pages 3 PIN NUMBERS 118, 119, 120 WE#, CAS#, RAS# 35, 37, 89, 92, 158, 160 CK0, CK0#, CK1, CK1#, CK2, CK2#, 95, ...

Page 5

... SS V Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. NC — No Connect: These pins should be left unconnected. 5 200-PIN DDR SODIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...

Page 6

... CK2 10pF 120Ω CK2# V REF V SS Standard modules use the following DDR SDRAM devices: MT46V16M16TG (256MB); MT46V32M16TG (512MB) Lead-free modules use the following DDR SDRAM devices: www.micron.com/num- MT46V16M16P (256MB); MT46V32M16P (512MB)) 6 200-PIN DDR SODIMM CS# LDQS UDQS LDM UDM DQ32 DQ DQ ...

Page 7

... DDR SDRAM modules use internally config- ured quad-bank DDR SDRAMs. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...

Page 8

A4–A6 specify the CAS latency, and A7–A12 specify the operating mode. Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being program- mable, as shown in Figure 4, Mode Register Definition ...

Page 9

Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES WITHIN LENGTH ADDRESS TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...

Page 10

... Output Drive Strength The normal full drive strength for all outputs is specified to be SSTL2, Class II. The x16 DDR SDRAM devices used in these modules support an option for reduced drive. The reduced drive option is intended for lighter load and point-to-point environments. For detailed information on output drive strength options, refer to 256Mb or 512Mb DDR SDRAM component data sheets ...

Page 11

Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, below, provide a general refer- ence of available commands. For a more detailed Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF ...

Page 12

Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...

Page 13

Table 12: I Specifications and Conditions – 256MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 17–20; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...

Page 14

Table 13: I Specifications and Conditions – 512MB DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 17–20; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...

Page 15

Table 14: Capacitance Note: 11; notes appear on pages 17–20 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address Input Capacitance: S#, CKE, CK, CK# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: ...

Page 16

Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12–15, 29; notes appear on pages 17–20; 0°C ≤ CHARACTERISTICS PARAMETER AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command ...

Page 17

Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...

Page 18

DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 QHS). The data valid window ...

Page 19

Figure 7: Pull-Down Characteristics 160 140 120 100 0.0 0.5 1 (V) (V) OUT OUT Figure 9: Reduced-Drive Pull-Down Characteristics 0.0 0.5 1.0 V ...

Page 20

Random addressing changing and 100 percent of data changing at every transfer. 44. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE ...

Page 21

Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...

Page 22

SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shwon in Figure 12, Data Validity, and Figure ...

Page 23

Table 16: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 17: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read ...

Page 24

Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...

Page 25

Table 20: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses ...

Page 26

Table 20: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 32 Address and Command Setup Time, 33 Address and Command Hold Time, 34 Data/Data Mask Input Setup Time, 35 Data/Data Mask Input Hold Time, ...

Page 27

Figure 16: 200-Pin DDR SODIMM Dimensions 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.096 (2.44) 0.039 (.99) 0.079 (2.00) PIN 1 U8 PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Released (No Mark): ...

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