MT8VDDT6464AY-40BF3 Micron Technology Inc, MT8VDDT6464AY-40BF3 Datasheet
MT8VDDT6464AY-40BF3
Specifications of MT8VDDT6464AY-40BF3
Related parts for MT8VDDT6464AY-40BF3
MT8VDDT6464AY-40BF3 Summary of contents
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DDR SDRAM Unbuffered DIMM MT8VDDT1664A – 128MB MT8VDDT3264A – 256MB MT8VDDT6464A – 512MB For the component specifications, refer to Micron’s Web site: Features • 184-pin dual in-line memory module (DIMM) • Fast data transfer rates: PC3200 • Utilizes 400 MT/s ...
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... MT8VDDT3264AG-40B__ 256MB MT8VDDT3264AY-40B__ 256MB 512MB MT8VDDT6464AG-40B__ MT8VDDT6464AY-40B__ 512MB Notes: 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult Micron for current revision codes. Example: MT8VDDT3264AG-40BC3. PDF: 09005aef80a43556, Source: 09005aef80a43534 DDA8C16_32_64x64AG_1.fm - Rev. E 4/06 EN 128MB, 256MB, 512MB (x64, SR): PC3200 184-Pin DDR UDIMM ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 184-Pin DIMM (MO-206 ...
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List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Assignments and Descriptions Table 3: Pin Assignment 184-Pin DIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ17 47 REF 2 DQ0 25 DQS2 ...
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Table 4: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information Pin Numbers 63, 65, 154 WE#, CAS#, RAS# 16, 17, 75, 76, 137, 138 CK0, CK0#, CK1, CK1#, ...
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... Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU – Do not use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. NC – No connect: These pins should be left unconnected. 8 Pin Assignments and Descriptions Description Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... Guide at www.micron.com/numberguide. Standard (lead-containing) modules use the following DDR SDRAM devices: MT46V16M8TG (128MB), MT46V32M8TG (256MB), and MT46V64M8TG (512MB). Lead- free modules use the following DDR SDRAM devices: MT46V16M8TP (128MB), MT46V32M8TP (256MB), and MT46V64M8TP (512MB). Figure 3: Functional Block Diagram – Standard PCB ...
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Figure 4: Functional Block Diagram – Low-Profile PCB S0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 ...
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... DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed opera- tion. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single ...
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Electrical Specifications Stresses greater than those listed Figure 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational ...
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Table 9: I Specifications and Conditions – 128MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 30; notes appear on pages 16–18; 0°C ≤ T Parameter/Condition Operating current: One device bank; Active-Precharge (MIN); ...
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Table 10: I Specifications and Conditions – 256MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 30; notes appear on pages 16–18; 0°C ≤ T Parameter/Condition Operating current: One device bank; Active-Precharge (MIN); ...
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Table 11: I Specifications and Conditions – 512MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 30; notes appear on pages 16–18; 0°C ≤ T Parameter/Condition Operating current: One device bank; Active-Precharge (MIN); ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: Output ...
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This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period ( standby). 17. To maintain a valid level, the transitioning edge of the input must: 17a. Sustain ...
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... Alternatively, V provided a minimum of 42Ω of series resistance is used between the V the input pin. 24. For -40B modules, I 25. Random addressing changing and 50 percent of data changing at every transfer. 26. Random addressing changing and 100 percent of data changing at every transfer. 27. CKE must be active (HIGH) during the entire time a refresh command is executed. ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7 and Figure ...
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Figure 7: Data Validity SCL SDA Figure 8: Definition of Start and Stop SCL SDA Figure 9: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver PDF: 09005aef80a43556, Source: 09005aef80a43534 DDA8C16_32_64x64AG_2.fm - Rev. E ...
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Table 13: EEPROM Device Select Code Most significant bit (b7) is sent first Select Code Memory area select code (two arrays) Protection register select code Table 14: EEPROM Operating Modes Mode RW Bit 1 Current address read Random address read ...
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Table 15: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input leakage current: ...
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Table 17: Serial Presence-Detect Matrix “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” Byte Description 0 Number of SPD bytes used by Micron 1 Total number of bytes in SPD device 2 Fundamental memory type 3 Number of row addresses ...
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Table 17: Serial Presence-Detect Matrix “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” Byte Description 41 MIN ACTIVE/AUTO REFRESH time, 42 MIN AUTO REFRESH-to-ACTIVE/AUTO REFRESH command period MAX cycle time, CK (MAX) 44 MAX DQS-DQ skew time, 45 ...
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Package Dimensions All dimensions in inches (millimeters); diagram is for reference only. Refer to the MO document for complete design dimen- sions. Figure 11: 184-Pin DIMM Dimensions – Standard PCB 0.079 (2.00) R (4X 0.098 (2.50) D (2X) ...
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Figure 12: 184-Pin DIMM Dimensions – Low-Profile PCB 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.087 (2.21) 0.050 (1.27) TYP. 0.039 (1.0) TYP. 0.115 (2.92) TYP. PIN 184 1.95 (49.53) 8000 S. ...