MT36HTF25672Y-80ED1 Micron Technology Inc, MT36HTF25672Y-80ED1 Datasheet
MT36HTF25672Y-80ED1
Specifications of MT36HTF25672Y-80ED1
Related parts for MT36HTF25672Y-80ED1
MT36HTF25672Y-80ED1 Summary of contents
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DDR2 SDRAM Registered DIMM (RDIMM) MT36HTF25672(P) – 2GB MT36HTF51272(P) – 4GB For the latest component data sheets, refer to Micron’s Web site: Features • 240-pin, registered dual in-line memory module • Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300, or PC2-6400 ...
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... MT36HTF51272(P)Y-53E__ MT36HTF51272(P)Y-40E__ Notes: 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT36HTF25672Y-667D1. 2. Data sheets for the base devices can be found at www.micron.com. PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb HTF36C256_512x72.fm - Rev. C 1/07 EN 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM ...
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Pin Assignments and Descriptions Table 5: Pin Assignments 240-Pin RDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ19 61 REF DQ0 33 DQ24 63 4 DQ1 34 ...
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Table 6: Pin Descriptions Symbol Type ODT0, ODT1 Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the (SSTL_18) DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#, and CB. The ODT ...
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Functional Block Diagrams Figure 2: Functional Block Diagram – 2GB V SS RS0# RS1# DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3# DQS8 DQS8# DQS4 DQS4# DQS5 DQS5# DQS6 DQS6# DQS7 DQS7# Rank 0 = U1–U5, U8–U16, U18–U21 Rank 1 ...
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Figure 3: Functional Block Diagram – 4GB V SS RS0# RS1# Rank 0 = U1–U5, U8–U16, U18–U21 Rank 1 = U22–U25, U27–U40 S0# S1# BA0–BA1 A0–A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 PAR_IN RESET# PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb HTF36C256_512x72.fm - ...
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... READs and by the memory controller during WRITEs. DQS is edge- aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. ...
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... Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’ ...
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I Specifications DD Table 9: DDR2 I Specifications and Conditions – 2GB DD Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the 512Mb (128 Meg x 4) component data sheet Parameter/Condition Operating one bank ...
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Table 10: DDR2 I Specifications and Conditions – 4GB DD Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) component data sheet Parameter/Condition Operating one bank active-precharge current: t ...
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Register and PLL Specifications Table 11: Register Specifications SSTU32868 devices or equivalent JESD82-14 for the 4GB and SSTU32866 devices or equivalent JESD82-10 for the 2GB Parameter Symbol DC high-level input voltage ...
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Table 12: PLL Specifications CU877 device or equivalent JESD82-8.01 Parameter Symbol DC high-level input voltage V DC low-level input voltage V Input voltage (limits high-level input voltage V DC low-level input voltage V Input differential-pair cross V voltage ...
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Serial Presence-Detect Table 14: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input ...
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Table 16: Serial Presence-Detect Matrix Byte Description 0 Number of SPD bytes used by Micron 1 Total number of bytes in SPD device 2 Fundamental memory type 3 Number of row addresses on SDRAM 4 Number of column addresses on ...
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Table 16: Serial Presence-Detect Matrix (continued) Byte Description 26 SDRAM access from CK, 27 MIN row precharge time, 28 MIN row active-to-row active, 29 MIN RAS#-to-CAS# delay, 30 MIN active-to-precharge time, 31 Module rank density 32 Address and command setup ...
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Table 16: Serial Presence-Detect Matrix (continued) Byte Description 45 SDRAM device MAX read data hold skew factor, t QHS 46 PLL relock time 47–61 Optional features, not supported 62 SPD revision 63 Checksum for bytes 0–62 ECC/ECC and Parity 64 ...
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Module Dimensions Figure 4: 240-Pin DDR2 RDIMM – 2GB 2.0 (0.079) R (4X) U12 U13 U14 2.50 (0.098) D (2X) 2.30 (0.091) TYP PIN 1 2.21 (0.087) TYP 1.0 (0.039) TYP 1.0 (0.039) TYP 70.66 (2.782) TYP ...
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Figure 5: 240-Pin DDR2 RDIMM – 4GB 2.0 (0.079 (4X) U12 U13 U14 2.50 (0.098) D (2X) 2.30 (0.091) TYP PIN 1 2.21 (0.087) TYP 1.0 (0.039) TYP 1.0 (0.039) TYP 70.66 (2.782) TYP U22 U23 ...