MODULE DDR2 1GB 240-DIMM

HYS64T128020HU-3S-B

Manufacturer Part NumberHYS64T128020HU-3S-B
DescriptionMODULE DDR2 1GB 240-DIMM
ManufacturerQimonda
HYS64T128020HU-3S-B datasheet
 


Specifications of HYS64T128020HU-3S-B

Memory TypeDDR2 SDRAMMemory Size1GB
Speed333MHzPackage / Case240-DIMM
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names675-1024
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December 2006
HYS64T32x00HU–[25F/2.5/3/3S/3.7/5]–B
HYS[64/72]T64x00HU–[25F/2.5/3/3S/3.7/5]–B
HYS[64/72]T128x20HU–[25F/2.5/3/3S/3.7/5]–B
2 4 0 - P i n u n b u f f e r e d D D R 2 S D R A M M o d u l e s
D D R 2 S D R A M
U D I M M S D R A M
R o H S C o m p l i a n t
I n t e r n e t D a t a S h e e t
R e v . 1 . 3

HYS64T128020HU-3S-B Summary of contents

  • Page 1

    HYS64T32x00HU–[25F/2.5/3/3S/3.7/5]–B HYS[64/72]T64x00HU–[25F/2.5/3/3S/3.7/5]–B HYS[64/72]T128x20HU–[25F/2.5/3/3S/3.7/5]– ...

  • Page 2

    ... Added WhiteBox Products for Speed Grade –3S and –3.7 to IDD tables. 70, 74, 78, Updated SPD codes for –3S and –3.7 WhiteBox Products. 82 Previous Revision: 2006-09, Rev. 1.21 All Qimonda update Previous Revision: 2006-06, Rev. 1.2 43 SPD codes updated Previous Revision: 2006-01, Rev. 1.1 3 ...

  • Page 3

    ... Overview This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main characteristics. 1.1 Features Feature list and performance tables • 240-Pin PC2–6400, PC2–5300, PC2–4200 and PC2–3200 DDR2 SDRAM memory modules. • 32M × 64, 64M × 64, 64M × 72, 128M × 64 and 128M ×72 module organization and 32M × ...

  • Page 4

    ... HYS64T64900HU–3S–B 512 MB 1R×8 PC2–5300U–555–12–D0 HYS72T64000HU–3S–B 512 MB 1R×8 PC2–5300E–555–12–F0 HYS64T128020HU–3S– 2R×8 PC2–5300U–555–12–E0 HYS64T128920HU–3S– 2R×8 PC2–5300U–555–12–E0 HYS72T128020HU–3S– 2R× ...

  • Page 5

    ... HYS64T64000HU–5–B 512 MB 1R×8 PC2–3200U–333–12–D0 HYS72T64000HU–5–B 512 MB 1R×8 PC2–3200E–333–12–F0 HYS64T128020HU–5– 2R×8 PC2–3200U–333–12–E0 HYS72T128020HU–5– 2R×8 PC2–3200E–333–12–G0 1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T64000HU–3.7–B, indicating Rev. ...

  • Page 6

    ... Product Type DRAM Components HYS64T32000HU HYB18T512160BF HYS64T32900HU HYS64T64000HU HYB18T512800BF HYS64T64900HU HYS72T64000HU HYB18T512800BF HYS64T128020HU HYB18T512800BF HYS64T128920HU HYS72T128020HU HYB18T512800BF 1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module ...

  • Page 7

    ... Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module and Table 7 respectively. The pin numbering is depicted in Figure 1 for non-ECC modules (×64) and modules (×72). Table 6 Function Clock Signals 2:0, Complement Clock Signals 2:0 Clock Enable Rank 1:0 Note: 2 Ranks module Not Connected ...

  • Page 8

    ... Note: 1 Gbit based module and 512M Not Connected × Note: Module based on 1 Gbit 16 × Module based on 512 Mbit 16 or smaller Address Signal 14 Note: Modules based on 2 Gbit Not Connected Note: Modules based on 1 Gbit or smaller Data Bus 63:0 Data Input/Output pins 8 Internet Data Sheet ...

  • Page 9

    Ball No. Name Pin Buffer Type Type 12 DQ8 I/O SSTL 13 DQ9 I/O SSTL 21 DQ10 I/O SSTL 22 DQ11 I/O SSTL 131 DQ12 I/O SSTL 132 DQ13 I/O SSTL 140 DQ14 I/O SSTL 141 DQ15 I/O SSTL 24 ...

  • Page 10

    Ball No. Name Pin Buffer Type Type 98 DQ48 I/O SSTL 99 DQ49 I/O SSTL 107 DQ50 I/O SSTL 108 DQ51 I/O SSTL 217 DQ52 I/O SSTL 218 DQ53 I/O SSTL 226 DQ54 I/O SSTL 227 DQ55 I/O SSTL 110 ...

  • Page 11

    Ball No. Name Pin Buffer Type Type 167 CB6 I/O SSTL NC NC — 168 CB7 I/O SSTL NC NC — Data Strobe Bus 7 DQS0 I/O SSTL 16 DQS1 I/O SSTL 28 DQS2 I/O SSTL 37 DQS3 I/O SSTL ...

  • Page 12

    ... Serial Address Select Bus 2:0 I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply Power Supply Ground Plane On-Die Termination Control 0 On-Die Termination Control 1 Note: 2 Rank modules Not Connected Note: 1 Rank modules Not connected Note: Pins not connected on Qimonda UDIMMs 12 Internet Data Sheet ...

  • Page 13

    Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low ...

  • Page 14

    Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module Pin Configuration UDIMM ×64 (240 Pin) 14 Internet Data Sheet FIGURE 1 ...

  • Page 15

    Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module Pin Configuration UDIMM ×72 (240 Pin) 15 Internet Data Sheet FIGURE 2 ...

  • Page 16

    Electrical Characteristics This chapter describes the Electrical Characteristics. 3.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Symbol Parameter V V Voltage on pin relative ...

  • Page 17

    DC Operating Conditions This chapter contains the DC Operating Conditions tables. Parameter Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative) 1) DRAM Component Case Temperature is the surface temperature in the ...

  • Page 18

    Timing Characteristics This chapter describes the AC Characteristics. 3.3.1 Speed Grade Definitions All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications( Speed Grade Definition for: DDR2–800(Table Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ ...

  • Page 19

    Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew ...

  • Page 20

    Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time 1) Timings are guaranteed with CK/CK differential Slew ...

  • Page 21

    ... Exit precharge power-down to any valid command (other than NOP or Deselect) Exit self-refresh to a non-read command Exit self-refresh to read command Write command to DQS associated clock edges 1) For details and notes see the relevant Qimonda component data sheet 1.8 V ± 0.1V 1.8 V ± 0.1 V. See notes ...

  • Page 22

    Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings ...

  • Page 23

    QH HP QHS HP max column. {The less half-pulse width distortion present, the larger the t Examples: ...

  • Page 24

    ... Exit precharge power-down to any valid command (other than NOP or Deselect) Exit self-refresh to a non-read command Exit self-refresh to read command Write command to DQS associated clock edges 1) For details and notes see the relevant Qimonda component data sheet 1.8 V ± 0.1V; = 1.8 V ± 0.1 V. See notes ...

  • Page 25

    New units, ‘ ‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘ CK.AVG under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and t ...

  • Page 26

    RPST RPRE begins driving ( ). Figure 3 RPST ...

  • Page 27

    Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module Method for calculating transitions and endpoint Differential input waveform timing - t Differential input waveform timing - t 27 Internet Data Sheet FIGURE 3 FIGURE 4 and FIGURE ...

  • Page 28

    Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...

  • Page 29

    ... Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command Write recovery time for write with Auto- Precharge 1) For details and notes see the relevant Qimonda component data sheet = 1.8 V ± 0 1.8 V ±0.1 V. See notes ...

  • Page 30

    The , and , parameters are referenced to a specific voltage level, which specify when the device output is no longer driving HZ RPST LZ RPRE begins ...

  • Page 31

    Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...

  • Page 32

    ... Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command Write recovery time for write with Auto- Precharge 1) For details and notes see the relevant Qimonda component data sheet = 1.8 V ± 0 1.8 V ±0.1 V. See notes ...

  • Page 33

    The , and , parameters are referenced to a specific voltage level, which specify when the device output is no longer driving HZ RPST LZ RPRE begins ...

  • Page 34

    ODT AC Character. and Operating Conditions for DDR2-533 & DDR2-400 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD t ODT turn-off AOF t ODT ...

  • Page 35

    I Specifications and Conditions DD I List of tables defining Specifications and Conditions. DD • Table 22 “IDD Measurement Conditions” on Page 35 • Table 23 “Definitions for IDD” on Page 36 • Table 25 “IDD Specification for HYS[64/72]T[32/64/128]0x0HU-2.5-B” ...

  • Page 36

    ... Definitions for see Table For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode 5) For details and notes see the relevant Qimonda component data sheet and current measurements are defined with the outputs disabled ( ...

  • Page 37

    Product Type Organization 256MB 512MB 1 Rank 1 Rank ×64 ×64 -25F -25F Symbol Max. Max. I 420 670 DD0 I 480 800 DD1 DD2P I 200 410 DD2N I 180 360 DD2Q I 160 310 DD3P( ...

  • Page 38

    Product Type Organization 256MB 1 Rank ×64 -2.5 Symbol Max. I 400 DD0 I 460 DD1 I 30 DD2P I 200 DD2N I 180 DD2Q I 160 DD3P( MRS = DD3P( MRS = 1) I 240 DD3N ...

  • Page 39

    Product Type Organization 256MB 512MB 1 Rank 1 Rank ×64 × Symbol Max. Max. I 380 600 DD0 I 420 720 DD1 DD2P I 180 360 DD2N I 160 320 DD2Q I 130 260 DD3P( ...

  • Page 40

    Product Type Organization 256MB 512MB 1 Rank 1 Rank ×64 ×64 -3S -3S Symbol Max. Max. I 360 570 DD0 I 400 680 DD1 DD2P I 180 360 DD2N I 160 320 DD2Q I 130 260 DD3P( ...

  • Page 41

    Product Type Organization 256MB 512MB 1 Rank 1 Rank ×64 ×64 -3.7 -3.7 Symbol Max. Max. I 320 520 DD0 I 360 600 DD1 DD2P I 150 300 DD2N I 140 280 DD2Q I 110 220 DD3P( ...

  • Page 42

    Product Type Organization 256MB 512MB 1 Rank 1 Rank ×64 × Symbol Max. Max. I 300 490 DD0 I 330 560 DD1 DD2P I 140 270 DD2N I 130 260 DD2Q I 100 190 DD3P( ...

  • Page 43

    SPD Codes This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which ...

  • Page 44

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 7 Not used 8 Interface Voltage Level (Byte 18) [ns] CK MAX t 10 SDRAM @ CL (Byte 18) [ns] AC MAX 11 Error Correction Support ...

  • Page 45

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 31 Module Density per Rank and [ns] AS.MIN CS.MIN and [ns] AH.MIN CH.MIN t 34 [ns] DS.MIN t 35 [ns] DH.MIN t 36 [ns] ...

  • Page 46

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ T (DT4R) / ∆ Sign (DT4R4W) 4R 4R4W ∆ (DT5B) 5B ∆ (DT7 Psi(ca) PLL 59 Psi(ca) REG ∆ ...

  • Page 47

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 79 Product Type, Char 7 80 Product Type, Char 8 81 Product Type, Char 9 82 Product Type, Char 10 83 Product Type, Char 11 84 Product Type, Char 12 ...

  • Page 48

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank ...

  • Page 49

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 21 DIMM Attributes 22 Component Attributes (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX ...

  • Page 50

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 45 [ns] QHS.MAX 46 PLL Relock Time T Delta / ∆ Delta CASE.MAX 4R4W 48 Psi(T-A) DRAM ∆ (DT0) 0 ∆ T (DT2N, UDIMM) or ...

  • Page 51

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 69 Manufacturer’s JEDEC ID Code (6) 70 Manufacturer’s JEDEC ID Code (7) 71 Manufacturer’s JEDEC ID Code (8) 72 Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, ...

  • Page 52

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number 99 - 127 Not used 128 - Blank for customer use 255 Rev. 1.3, ...

  • Page 53

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank ...

  • Page 54

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 22 Component Attributes (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] ...

  • Page 55

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 46 PLL Relock Time Delta / ∆ Delta CASE.MAX 4R4W 48 Psi(T-A) DRAM ∆ (DT0) 0 ∆ T (DT2N, UDIMM) or ∆ ...

  • Page 56

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 70 Manufacturer’s JEDEC ID Code (7) 71 Manufacturer’s JEDEC ID Code (8) 72 Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char ...

  • Page 57

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 94 Module Manufacturing Date Week Module Serial Number 99 - 127 Not used 128 - Blank for customer use 255 Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 ...

  • Page 58

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank ...

  • Page 59

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] CK MAX t ...

  • Page 60

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT0) 0 ∆ T (DT2N, UDIMM) or ∆ ∆ (DT2P) 2P ∆ (DT3N) 3N ∆ (DT3P fast) ...

  • Page 61

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 ...

  • Page 62

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank ...

  • Page 63

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] CK MAX t ...

  • Page 64

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT0) 0 ∆ T (DT2N, UDIMM) or ∆ ∆ (DT2P) 2P ∆ (DT3N) 3N ∆ (DT3P fast) ...

  • Page 65

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 ...

  • Page 66

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank ...

  • Page 67

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] CK MAX t ...

  • Page 68

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT0) 0 ∆ (DT2N, UDIMM) or ∆ ∆ (DT2P) 2P ∆ (DT3N) 3N ∆ (DT3P fast) ...

  • Page 69

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 ...

  • Page 70

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank ...

  • Page 71

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] CK MAX t ...

  • Page 72

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT0) 0 ∆ (DT2N, UDIMM) or ∆ ∆ (DT2P) 2P ∆ (DT3N) 3N ∆ (DT3P fast) ...

  • Page 73

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 ...

  • Page 74

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank ...

  • Page 75

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 22 Component Attributes (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] ...

  • Page 76

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 46 PLL Relock Time Delta / ∆ Delta CASE.MAX 4R4W 48 Psi(T-A) DRAM ∆ (DT0) 0 ∆ T (DT2N, UDIMM) or ∆ ...

  • Page 77

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 70 Manufacturer’s JEDEC ID Code (7) 71 Manufacturer’s JEDEC ID Code (8) 72 Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char ...

  • Page 78

    Product Type Organization Label Code JEDEC SPD Revision Byte# Description 94 Module Manufacturing Date Week Module Serial Number 99 - 127 Not used 128 - Blank for customer use 255 Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 ...

  • Page 79

    Package Outlines This chapter contains the Package Outline tables. Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module Package Outline Raw Card C ...

  • Page 80

    Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module Package Outline Raw Card D L-DIM-240-8 80 Internet Data Sheet FIGURE 7 ...

  • Page 81

    Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module Package Outline Raw Card E L-DIM-240-9 81 Internet Data Sheet FIGURE 8 ...

  • Page 82

    Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module Package Outline Raw Card F L-DIM-240-6 82 Internet Data Sheet FIGURE 9 ...

  • Page 83

    Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2006-12 03292006-6GMD-RSFT HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B Unbuffered DDR2 SDRAM Module Package Outline Raw Card G L-DIM-240-7 83 Internet Data Sheet FIGURE 10 ...

  • Page 84

    ... Product Type Nomenclature Qimonda’s nomenclature uses simple coding combined with some propriatory coding. Table 38 provides examples for module and component product type number as well as the Example for Field Number 1 2 Micro-DIMM HYS 64 DDR2 DRAM HYB 18 Field Description 1 Qimonda Module Prefix ...

  • Page 85

    ... Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. Field Description 1 Qimonda Component Prefix 2 Interface Voltage [V] 3 DRAM Technology ...

  • Page 86

    Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 87

    ... With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. ...