HYS64T128020HU-3S-B Qimonda, HYS64T128020HU-3S-B Datasheet - Page 23

MODULE DDR2 1GB 240-DIMM

HYS64T128020HU-3S-B

Manufacturer Part Number
HYS64T128020HU-3S-B
Description
MODULE DDR2 1GB 240-DIMM
Manufacturer
Qimonda
Datasheet

Specifications of HYS64T128020HU-3S-B

Memory Type
DDR2 SDRAM
Memory Size
1GB
Speed
333MHz
Package / Case
240-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
675-1024
26)
27)
28)
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support
32)
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Parameter
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated DQ signals
DQS latching rising transition to associated clock
edges
t
max column. {The less half-pulse width distortion present, the larger the
Examples: 1) If the system provides
provides
t
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
t
(
driving (
calculation is consistent.
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
t
QH
QHS
RPST
t
nRP
WTR
RPST
t
t
JIT.PER.MAX
JIT.DUTY.MAX
=
t
t
= RU{
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
is at lease two clocks (2 x
JIT.PER.MAX
JIT.DUTY.MAX
t
end point and
), or begins driving (
HP
t
RPRE
t
HP
t
t
RP
QHS
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
= 1.1 x
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
/
= 0.6 x
, where:
= + 93 ps, then
t
CK.AVG
= + 93 ps, then
t
t
RPRE
CK.AVG
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
CK.AVG
t
HP
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
t
RPRE
is the minimum of the absolute half period of the actual input clock; and
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
t
).
RPRE.MIN(DERATED)
t
t
RPST.MIN(DERATED)
CK
Figure 3
) independent of operation frequency.
t
HP
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
shows a method to calculate these points when the device is no longer driving (
=
DRAM Component Timing Parameter by Speed Grade - DDR2–667
=
t
RPRE.MIN
t
RPST.MIN
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH.AVG
CK.AVG
CKE
CL.AVG
DAL
DELAY
DH.BASE
DIPW
DQSCK
DQSH
DQSL
DQSQ
DQSS
+
+
t
t
JIT.PER.MIN
JIT.DUTY.MIN
23
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
= 0.9 x
= 0.4 x
t
DDR2–667
–450
2
0.48
3000
3
0.48
WR +
t
t
175
0.35
–400
0.35
0.35
– 0.25
QH
t
Min.
IS
IH
QH
+
of 1080 ps minimum.
value is; and the larger the valid data eye will be.}
t
t
CK.AVG
CK .AVG
t
CK.AVG
t
nRP
– 72 ps = + 2178 ps and
– 72 ps = + 928 ps and
+
t
nPARAM
Max.
+450
0.52
8000
0.52
+400
240
+ 0.25
Unbuffered DDR2 SDRAM Module
= RU{
t
t
QHS
QH
t
t
of 975 ps minimum. 2) If the system
JIT.PER
JIT.DUTY
t
is the specification value under the
t
nRP
RP
t
PARAM
= 15 ns, the device will support
= RU{
of the input clock. (output
t
of the input clock. (output
t
RPRE.MAX(DERATED)
RPST.MAX(DERATED)
Unit
ps
nCK
t
ps
nCK
t
nCK
ns
ps
t
ps
t
t
ps
t
/
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
t
CK.AVG
t
Internet Data Sheet
t
RP
HP
/
t
t
at the input is
JIT.DUTY.MIN
JIT.PER.MIN
t
TABLE 17
CK.AVG
}, which is in clock
Note
1)2)3)4)5)6)7)8)
9)
10)11)
12)
10)11)
13)14)
19)20)15)
9)
16)
17)
t
RPST
}, which is in
), or begins
=
=
= – 72 ps
= – 72 ps
t
t
RPRE.MAX
RPST.MAX

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