HYS64T128020HU-3S-B Qimonda, HYS64T128020HU-3S-B Datasheet - Page 3

MODULE DDR2 1GB 240-DIMM

HYS64T128020HU-3S-B

Manufacturer Part Number
HYS64T128020HU-3S-B
Description
MODULE DDR2 1GB 240-DIMM
Manufacturer
Qimonda
Datasheet

Specifications of HYS64T128020HU-3S-B

Memory Type
DDR2 SDRAM
Memory Size
1GB
Speed
333MHz
Package / Case
240-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
675-1024
1
This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Feature list and performance tables
• 240-Pin PC2–6400, PC2–5300, PC2–4200 and
• 32M × 64, 64M × 64, 64M × 72, 128M × 64 and 128M ×72
• Standard Double-Data-Rate-Two Synchronous DRAMs
• 256MB, 512MB and 1GB modules built with 512-Mbit
• All speed grades faster than DDR2–400 comply with
• Programmable CAS Latencies (3, 4 and 5),
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Product Type Speed Code
Speed Grade
Max. Clock Frequency
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
PC2–3200 DDR2 SDRAM memory modules.
module organization and 32M × 16, 64M × 8 chip
organization
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
DDR2 SDRAMs in P-TFBGA-84 and P-TFBGA-60
chipsize packages
DDR2–400 timing specifications.
Burst Length (8 & 4) and Burst Type
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Overview
Features
@CL6
@CL5
@CL4
@CL3
f
f
f
f
t
t
t
t
CK6
CK5
CK4
CK3
RCD
RP
RAS
RC
–25F
PC2–6400
5–5–5
400
400
266
200
12.5
12.5
45
57.5
–2.5
PC2–6400
6–6–6
400
333
266
200
15
15
45
60
3
• Auto Refresh (CBR) and Self Refresh
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• Average Refresh Period 7.8 µs at a
• DCC enabling via EMRS2 setting
• All inputs and outputs SSTL_1.8 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and
• Serial Presence Detect with E
• UDIMM Dimensions (nominal):
• Based on standard reference layouts Raw Card “C”,
• RoHS compliant products
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
–3
PC2–5300
4–4–4
333
333
200
12
12
45
57
85 °C, 3.9µs between 85 °C and 95 °C.
On-Die Termination (ODT)
30 mm high, 133.35 mm wide
“D”,”E”,”F” and “G“
–3S
PC2–5300
5–5–5
333
266
200
15
15
45
60
Unbuffered DDR2 SDRAM Module
–3.7
PC2–4200
4–4–4
266
266
200
15
15
45
60
1)
2
PROM
Performance Table
Internet Data Sheet
T
200
200
200
–5
PC2–3200
3–3–3
15
15
40
55
CASE
lower than
TABLE 1
Unit
MHz
MHz
MHz
MHz
ns
ns
ns
ns

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