HYS64T128020HU-3S-B Qimonda, HYS64T128020HU-3S-B Datasheet - Page 36

• Manufacturer Part Number: HYS64T128020HU-3S-B
• Description: MODULE DDR2 1GB 240-DIMM
• Manufacturer: Qimonda

Specifications of HYS64T128020HU-3S-B

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 333MHz
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1024

1)
2)
3) Definitions for
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode
5) For details and notes see the relevant Qimonda component data sheet
6)
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Parameter
Burst Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING.
All Bank Interleave Read Current
All banks are being interleaved at minimum
and address bus inputs are STABLE during DESELECTS.
Parameter
LOW
STABLE
FLOATING
SWITCHING
CK
CK
V
I
I
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
=
=
DD
DD1
DDQ
t
t
CK.MIN
CK.MIN.
specifications are tested after the device is properly initialized and
,
I
= 1.8 V ± 0.1 V;
DD4R
., Refresh command every
, Refresh command every
and
I
I
DD
Description
V
Inputs are stable at a HIGH or LOW level
Inputs are
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
DD7
IN
see
current measurements are defined with the outputs disabled (
≤
V
V
Table 23
DD
IL(ac).MAX
= 1.8 V ± 0.1 V
V
I
DD6
REF
, HIGH is defined as
current values are guaranteed up to
=
V
DDQ
t
t
RFC
RFC
/2
=
=
t
RC
t
t
REFI
RFC.MIN
without violating
interval, CKE is LOW and CS is HIGH between valid
V
interval, CKE is HIGH, CS is HIGH between valid
IN
≥
V
I
IH(ac).MIN
out
36
= 0 mA.
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
t
RRD
I
DD
T
parameter are specified with ODT disabled.
using a burst length of 4. Control
CASE
I
of 85 °C max.
OUT
= 0 mA). To achieve this on module level the output
Unbuffered DDR2 SDRAM Module
I
DD2P
Definitions for I
Internet Data Sheet
Symbol Note
I
I
I
I
DD5B
DD5D
DD6
DD7
TABLE 23
1)2)3)4)5)
6)
DD