HDSP-2502 Avago Technologies US Inc., HDSP-2502 Datasheet - Page 12

• Manufacturer Part Number: HDSP-2502
• Description: LED DISPLAY 5X7 8CHAR 7MM HE RED
• Manufacturer: Avago Technologies US Inc.
• Series: HDSP-250xr

Specifications of HDSP-2502

• Display Type: Alphanumeric
• Package / Case: 28-DIP
• Color: Red
• Size / Dimension: 1.68" L x 0.77" W x 0.21" H (42.59mm x 19.58mm x 5.31mm)
• Number Of Digits/alpha: 8
• Common Pin: *
• Digit/alpha Size: 0.27" (7mm)
• Number Of Digits: 8
• Character Size: 5 mm x 7 mm
• Illumination Color: Red
• Wavelength: 635 nm
• Operating Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Luminous Intensity: 7.5 mcd
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1164-5

UDC RAM and UDC Address Register
Figure 3 shows the logic levels needed to access the UDC
RAM and the UDC Address Register. The UDC Address
Register is eight bits wide. The lower four bits (D
used to select one of the 16 UDC locations. The upper
four bits (D
been stored in the UDC Address Register, the UDC RAM
can be accessed.
To completely specify a 5 x 7 character, eight write cycles
are required. One cycle is used to store the UDC RAM
address in the UDC Address Register and seven cycles are
used to store dot data in the UDC RAM. Data is entered by
rows and one cycle is needed to access each row. Figure 4
shows the organization of a UDC character assuming the
symbol to be stored is an “F. ” A
row to be accessed and D
row dot data. The upper three bits (D
D
column of the 5 x 7 matrix and D
corresponds to the left most column of the 5 x 7 matrix.
Flash RAM
Figure 5 shows the logic levels needed to access the
Flash RAM. The Flash RAM has one bit associated with
each location of the Character RAM. The Flash input is
used to select the Flash RAM while address lines A
are ignored. Address lines A
loca tion in the Flash RAM to store the attri bute. D
to store or remove the flash attribute. D
attribute and D
When the attribute is enabled through bit 3 of the
Control Word and a “1” is stored in the Flash RAM, the
corresponding character will flash at approxi mately 2
Hz. The actual rate is dependent on the clock fre quency.
For an external clock the flash rate can be calculated by
dividing the clock frequency by 28,672.
12
0
(least signifi cant bit) corresponds to the right most
4
-D
7
) are not used. Once the UDC address has
0
= “0” removes the attribute.
0
-D
0
-A
4
0
-A
are used to transmit the
2
2
4
are used to select the
are used to select the
(most significant bit)
5
-D
0
= “1” stores the
7
) are ignored.
0
0
-D
is used
3
) are
3
-A
4
Figure 3. Logic levels to access a UDC character.
Figure 4. Data to load “”F’’ into the UDC RAM.
CONTROL SIGNALS
UDC ADDRESS REGISTER ADDRESS
UDC ADDRESS REGISTER DATA FORMAT
CONTROL SIGNALS
UDC RAM ADDRESS
UDC RAM
DATA FORMAT
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
C C C C C
O O O O O
L L L L L
1 2 3 4 5
D
1 1 1 1 1
1 0 0 0 0
1 0 0 0 0
1 1 1 1 0
1 0 0 0 0
1 0 0 0 0
1 0 0 0 0
IGNORED
RST
RST
4
D
D
FL
FL
1
1
X
1
1
X
D
0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED
7
7
3
D
2
CE
CE
A
D
A
D
X
X
0
0
0
0
4
4
6
6
D
1
D
WR
WR
0
A
D
A
D
0
0
1
1
0
X
0
0
1
1
1
X
3
3
5
5
RD
RD
A
A
X
D
D
C
O
L
1
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
0
1
0
1
X
0
1
0
1
2
2
4
ROW SELECT
4
UNDEFINED
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
UNDEFINED
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
A
A
D
D
X
1
1
3
3
DOT DATA
UDC CHARACTER
•
•
•
•
•
•
•
UDC CODE
A
A
X
D
D
•
•
0
0
2
2
•
•
000 = ROW 1
110 = ROW 7
D
D
•
•
1
1
•
D
D
C
O
L
5
0
0
HEX CODE
1F
10
10
1D
10
10
10