DAUGHT BOARD T610 32TQFP SOCKET

C8051T610DB32

Manufacturer Part NumberC8051T610DB32
DescriptionDAUGHT BOARD T610 32TQFP SOCKET
ManufacturerSilicon Laboratories Inc
C8051T610DB32 datasheet
 

Specifications of C8051T610DB32

Module/board TypeSocket Module - TQFPProcessor To Be EvaluatedC8051T61x
Interface TypeUSBLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use With/related ProductsC8051T610DKOther names336-1505
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Analog Peripherals
-
10-Bit ADC (‘T610/1/2/3/6 only)
Up to 500 ksps
Up to 21, 17, or 13 external inputs
VREF from external pin, Internal Regulator or V
Internal or external start of conversion source
Built-in temperature sensor
-
Comparators
Programmable hysteresis and response time
Configurable as interrupt sources
Configurable as reset source (Comparator 0)
Low current (<0.5 µA)
On-Chip Debug
C8051F310 can be used as code development 
-
platform; Complete development kit available
On-chip debug circuitry facilitates full speed, 
-
non-intrusive in-system debug
Provides breakpoints, single stepping, 
-
inspect/modify memory and registers
Supply Voltage 1.8 to 3.6 V
-
On-chip LDO for internal core supply
-
Built-in voltage supply monitor
Memory
-
1280 Bytes internal data RAM (256 + 1024)
-
16 or 8 kB byte-programmable EPROM code mem-
ory
Temperature Range: –40 to +85 °C
A
M
U
X
TEMP
SENSOR
C8051T610/1/2/3/6 only
PROGRAMMABLE PRECISION INTERNAL
16 kB/8 kB
EPROM
INTERRUPTS
Rev 1.0 2/09
C8051T610/1/2/3/4/5/6/7
Mixed-Signal Byte-Programmable EPROM MCU
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-
Up to 25 MIPS throughput with 25 MHz clock
DD
-
Expanded interrupt handler
Digital Peripherals
-
29/25/21 Port I/O with high sink current capability
-
Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
-
Four general purpose 16-bit counter/timers
-
16-Bit programmable counter array (PCA) with five
capture/compare modules and PWM functionality
Clock Sources
-
Internal oscillator: 24.5 MHz with ±2% accuracy
supports crystal-less UART operation
-
External oscillator: RC, C, or CMOS Clock
-
Can switch between clock sources on-the-fly; useful
in power saving modes
Packages
-
32-pin LQFP (C8051T610/2/4)
-
28-pin QFN (C8051T611/3/5)
-
24-pin QFN (C8051T616/7)
ANALOG
PERIPHERALS
UART
SMBus
10-bit
+
SPI
500 ksps
-
PCA
ADC
+
Timer 0
-
Timer 1
Timer 2
VOLTAGE
COMPARATORS
Timer 3
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
14
DEBUG
CIRCUITRY
Copyright © 2009 by Silicon Laboratories
DIGITAL I/O
Port 0
Port 1
Port 2
Port 3
1280 B
SRAM
POR
WDT
C8051T610/1/2/3/4/5/6/7

C8051T610DB32 Summary of contents

  • Page 1

    Analog Peripherals - 10-Bit ADC (‘T610/1/2/3/6 only 500 ksps • 21, 17 external inputs • VREF from external pin, Internal Regulator or V • Internal or external start of conversion source • Built-in temperature ...

  • Page 2

    C8051T610/1/2/3/4/5/6/7 2 Rev 1.0 ...

  • Page 3

    Table of Contents 1. System Overview ..................................................................................................... 15 2. Ordering Information ............................................................................................... 19 3. Pin Definitions.......................................................................................................... 20 4. LQFP-32 Package Specifications ........................................................................... 25 5. QFN-28 Package Specifications ............................................................................. 27 6. QFN-24 Package Specifications ............................................................................. 29 7. Electrical Characteristics ........................................................................................ 31 ...

  • Page 4

    C8051T610/1/2/3/4/5/6/7 16.2. Interrupt Register Descriptions ........................................................................ 87 16.3. External Interrupts INT0 and INT1................................................................... 92 17. EPROM Memory ..................................................................................................... 94 17.1. Programming and Reading the EPROM Memory ........................................... 94 17.1.1. EPROM Write Procedure ........................................................................ 94 17.1.2. EPROM Read Procedure........................................................................ 95 17.2. ...

  • Page 5

    Arbitration.............................................................................................. 134 22.3.3. Clock Low Extension............................................................................. 134 22.3.4. SCL Low Timeout.................................................................................. 134 22.3.5. SCL High (SMBus Free) Timeout ......................................................... 135 22.4. Using the SMBus........................................................................................... 135 22.4.1. SMBus Configuration Register.............................................................. 135 22.4.2. SMB0CN Control Register .................................................................... 139 22.4.3. Data Register ...

  • Page 6

    C8051T610/1/2/3/4/5/6/7 26.2. PCA0 Interrupt Sources................................................................................. 192 26.3. Capture/Compare Modules ........................................................................... 193 26.3.1. Edge-triggered Capture Mode............................................................... 194 26.3.2. Software Timer (Compare) Mode.......................................................... 195 26.3.3. High-Speed Output Mode ..................................................................... 196 26.3.4. Frequency Output Mode ....................................................................... 197 26.3.5. 8-bit Pulse Width Modulator Mode ...

  • Page 7

    List of Figures 1. System Overview Figure 1.1. C8051T610/2/4 Block Diagram (32-pin LQFP) ..................................... 16 Figure 1.2. C8051T611/3/5 Block Diagram (28-pin QFN) ....................................... 17 Figure 1.3. C8051T616/7 Block Diagram (24-pin QFN) .......................................... 18 3. Pin Definitions Figure 3.1. LQFP-32 Pinout ...

  • Page 8

    C8051T610/1/2/3/4/5/6/7 19. Reset Sources Figure 19.1. Reset Sources ................................................................................... 100 Figure 19.2. Power-On and VDD Monitor Reset Timing ....................................... 101 20. Oscillators and Clock Selection Figure 20.1. Oscillator Options .............................................................................. 106 21. Port Input/Output Figure 21.1. Port I/O Functional Block ...

  • Page 9

    Figure 25.4. Timer 2 16-Bit Mode Block Diagram ................................................. 180 Figure 25.5. Timer 2 8-Bit Mode Block Diagram ................................................... 181 Figure 25.6. Timer 3 16-Bit Mode Block Diagram ................................................. 185 Figure 25.7. Timer 3 8-Bit Mode Block Diagram ................................................... 186 ...

  • Page 10

    C8051T610/1/2/3/4/5/6/7 List of Tables 2. Ordering Information Table 2.1. Product Selection Guide ......................................................................... 19 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T610/1/2/3/4/5/6/7 ..................................... 20 4. LQFP-32 Package Specifications Table 4.1. LQFP-32 Package Dimensions .............................................................. 25 Table 4.2. LQFP-32 ...

  • Page 11

    UART0 Table 23.1. Timer Settings for Standard Baud Rates  Using The Internal 24.5 MHz Oscillator .............................................. 156 Table 23.2. Timer Settings for Standard Baud Rates  Using an External 22.1184 MHz Oscillator ......................................... 156 24. Enhanced Serial Peripheral ...

  • Page 12

    C8051T610/1/2/3/4/5/6/7 List of Registers SFR Definition 8.1. ADC0CF: ADC0 Configuration ...................................................... 43 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB .................................................... 44 SFR Definition 8.3. ADC0L: ADC0 Data Word LSB ...................................................... 44 SFR Definition 8.4. ADC0CN: ADC0 Control ................................................................ 45 ...

  • Page 13

    SFR Definition 21.6. P0SKIP: Port 0 Skip ................................................................... 126 SFR Definition 21.7. P1: Port 1 ................................................................................... 126 SFR Definition 21.8. P1MDIN: Port 1 Input Mode ....................................................... 127 SFR Definition 21.9. P1MDOUT: Port 1 Output Mode ................................................ 127 SFR Definition 21.10. ...

  • Page 14

    C8051T610/1/2/3/4/5/6/7 C2 Register Definition 27.1. C2ADD: C2 Address ...................................................... 208 C2 Register Definition 27.2. DEVICEID: C2 Device ID ............................................... 209 C2 Register Definition 27.3. REVID: C2 Revision ID .................................................. 209 C2 Register Definition 27.4. DEVCTL: C2 Device Control .......................................... 210 ...

  • Page 15

    System Overview C8051T610/1/2/3/4/5/6/7 devices are fully integrated, mixed-signal, system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering num- bers. High-speed pipelined 8051-compatible microcontroller core ( MIPS)  ...

  • Page 16

    C8051T610/1/2/3/4/5/6/7 Power On CIP-51 8051 Reset Controller Core Reset 8/16 k Byte EPROM Program Memory Debug / C2CK/RST Programming Hardware 256 byte SRAM C2D 1 k Byte XRAM Peripheral Power VDD Regulator Core Power GND EXTCLK External Clock Circuit System ...

  • Page 17

    Power On CIP-51 8051 Reset Controller Core Reset 8/16 k Byte EPROM Program Memory Debug / C2CK/RST Programming Hardware 256 byte SRAM C2D 1 k Byte XRAM Peripheral Power SYSCLK VDD Regulator Core Power GND EXTCLK External Clock Circuit System ...

  • Page 18

    C8051T610/1/2/3/4/5/6/7 Power On CIP-51 8051 Reset Controller Core Reset 16 k Byte EPROM Program Memory Debug / C2CK/RST Programming Hardware 256 byte SRAM C2D 1 k Byte XRAM Peripheral Power VDD Regulator Core Power GND EXTCLK External Clock Circuit System ...

  • Page 19

    Ordering Information Table 2.1. Product Selection Guide C8051T610-GQ 25 16k* 1280 C8051T611-GM 25 16k* 1280 C8051T612- 1280 C8051T613- 1280 C8051T614- 1280 C8051T615- 1280 C8051T616-GM 25 16k* 1280 C8051T617-GM 25 16k* 1280 ...

  • Page 20

    C8051T610/1/2/3/4/5/6/7 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T610/1/2/3/4/5/6/7 Pin Pin Name T610/2/4 T611/3/5 T616 GND 3 3 RST C2CK P3. C2D P0 P0 P0.2/ 32 ...

  • Page 21

    Table 3.1. Pin Definitions for the C8051T610/1/2/3/4/5/6/7 (Continued) Pin Pin Pin Name T610/2/4 T611/3/5 T616 P2.3 ...

  • Page 22

    C8051T610/1/2/3/4/5/6/7 P0 P0.0 3 GND 4 VDD 5 RST/C2CK 6 P3.0/C2D P3 P3.2 Figure 3.1. LQFP-32 Pinout Diagram (Top View) 22 C8051T610/2/4 Top View Rev 1.0 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 ...

  • Page 23

    P0.1 1 P0.0 2 GND 3 C8051T611/3/5 VDD 4 RST/C2CK 5 P3.0/C2D 6 P2.7 7 Figure 3.2. QFN-28 Pinout Diagram (Top View) C8051T610/1/2/3/4/5/6/7 Top View GND (optional) Rev 1.0 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 ...

  • Page 24

    C8051T610/1/2/3/4/5/6/7 P0.1 1 P0.0 2 GND 3 VDD 4 RST/C2CK 5 P3.0 / C2D 6 Figure 3.3. QFN-24 Pinout Diagram (Top View) 24 C8051T616/7 Top View GND (optional) Rev 1.0 18 P1.0 17 P1.1 16 P1.2 15 P1.3 14 P1.4 ...

  • Page 25

    LQFP-32 Package Specifications Figure 4.1. LQFP-32 Package Drawing Table 4.1. LQFP-32 Package Dimensions Dimension Min Typ A — — A1 0.05 — A2 1.35 1.40 b 0.30 0.37 c 0.09 — D 9.00 BSC. D1 7.00 BSC. e 0.80 ...

  • Page 26

    C8051T610/1/2/3/4/5/6/7 Figure 4.2. LQFP-32 Recommended PCB Land Pattern Table 4.2. LQFP-32 PCB Land Pattern Dimesions Dimension Min C1 8.40 C2 8.40 E 0.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern ...

  • Page 27

    QFN-28 Package Specifications Figure 5.1. QFN-28 Package Drawing Table 5.1. QFN-28 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 A3 0.25 REF b 0.18 0.23 D 5.00 BSC. D2 2.90 3.15 e 0.50 BSC. E 5.00 ...

  • Page 28

    C8051T610/1/2/3/4/5/6/7 Figure 5.2. QFN-28 Recommended PCB Land Pattern Table 5.2. QFN-28 PCB Land Pattern Dimesions Dimension Min C1 4.80 C2 4.80 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...

  • Page 29

    QFN-24 Package Specifications Figure 6.1. QFN-24 Package Drawing Table 6.1. QFN-24 Package Dimensions Dimension Min Typ A 0.70 0.75 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC. D2 2.55 2.70 e 0.50 BSC. E 4.00 BSC. E2 2.55 ...

  • Page 30

    C8051T610/1/2/3/4/5/6/7 Figure 6.2. QFN-24 Recommended PCB Land Pattern Table 6.2. QFN-24 PCB Land Pattern Dimesions Dimension Min C1 3.90 C2 3.90 E 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. ...

  • Page 31

    Electrical Characteristics 7.1. Absolute Maximum Specifications Table 7.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on RST or any Port I/O Pin (except V during programming) with PP respect to GND Voltage on V with ...

  • Page 32

    C8051T610/1/2/3/4/5/6/7 7.2. Electrical Characteristics Table 7.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Supply Voltage (Note 1) Regulator in Normal Mode Regulator in Bypass Mode Digital Supply Current with V DD CPU ...

  • Page 33

    Table 7.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Output High Voltage I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull ...

  • Page 34

    C8051T610/1/2/3/4/5/6/7 Table 7.4. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current RST = 0 POR ...

  • Page 35

    Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified. Use factory-calibrated settings Parameter Oscillator Frequency IFCN = 11b Oscillator Supply Current  25 °C, V ...

  • Page 36

    C8051T610/1/2/3/4/5/6/7 Table 7.9. Temperature Sensor Electrical Characteristics V – +85 °C unless otherwise specified. DD Parameter Linearity Slope Slope Error* Offset Offset Error* Note: Represents one standard deviation from the mean. Table 7.10. Voltage Reference ...

  • Page 37

    Table 7.11. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: CP0+ – CP0– = 100 mV * Mode 0, Vcm = 1.5 V CP0+ – CP0– = –100 mV Response ...

  • Page 38

    C8051T610/1/2/3/4/5/6/7 7.3. Typical Performance Curves 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) 2.5 2.0 1.5 1.0 0.5 0 Figure 7.2. Idle Mode ...

  • Page 39

    ADC (ADC0, C8051T610/1/2/3/6 only) ADC0 on the C8051T610/1/2/3 500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain stage programmable 0.5x, and a programmable window detector. The ADC is fully configurable under ...

  • Page 40

    C8051T610/1/2/3/4/5/6/7 8.1. Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. ...

  • Page 41

    Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left at ...

  • Page 42

    C8051T610/1/2/3/4/5/6/7 8.3.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling ...

  • Page 43

    SFR Definition 8.1. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following ...

  • Page 44

    C8051T610/1/2/3/4/5/6/7 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read 000000b. Bits ...

  • Page 45

    SFR Definition 8.4. ADC0CN: ADC0 Control Bit 7 6 AD0EN AD0TM AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ...

  • Page 46

    C8051T610/1/2/3/4/5/6/7 8.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code ...

  • Page 47

    SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte ...

  • Page 48

    C8051T610/1/2/3/4/5/6/7 8.4.1. Window Detector Example Figure 8.4 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit ...

  • Page 49

    ADC0 Analog Multiplexer (C8051T610/1/2/3/6 only) ADC0 on the C8051T610/1/2/3/6 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 1, 2 and 3 I/O ...

  • Page 50

    C8051T610/1/2/3/4/5/6/7 SFR Definition 8.9. AMX0P: AMUX0 Positive Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xBB Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 Positive Input ...

  • Page 51

    Temperature Sensor (C8051T610/1/2/3/6 only) An on-chip temperature sensor is included on the C8051T610/1/2/3/6 which can be directly accessed via the ADC multiplexer. To use the ADC to measure the temperature sensor, the ADC mux channel should be configured to ...

  • Page 52

    C8051T610/1/2/3/4/5/6/7 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 9.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius 52 0.00 20.00 40.00 Temperature (degrees C) Rev 1.0 5.00 4.00 3.00 2.00 1.00 0.00 ...

  • Page 53

    SFR Definition 9.1. TOFFH: Temperature Offset Measurement High Byte Bit 7 6 Name Type Varies Varies Varies Reset SFR Address = 0x86 Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Order Bits. The temperature sensor offset registers represent the output ...

  • Page 54

    C8051T610/1/2/3/4/5/6/7 10. Voltage Reference Options The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage refer- ence, the unregulated power supply voltage (V The REFSL bit in the Reference Control register (REF0CN, SFR Definition 10.1) ...

  • Page 55

    SFR Definition 10.1. REF0CN: Reference Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xD1 Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4 REGOVR Regulator Reference Override. This bit “overrides” ...

  • Page 56

    C8051T610/1/2/3/4/5/6/7 11. Voltage Regulator (REG0) C8051T610/1/2/3/4/5/6/7 devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a V supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to ...

  • Page 57

    SFR Definition 11.1. REG0CN: Voltage Regulator Control Bit 7 6 STOPCF BYPASS Name R/W R/W Type 0 0 Reset SFR Address = 0xC7 Bit Name 7 STOPCF Stop Mode Configuration. This bit configures the regulator’s behavior when the device enters ...

  • Page 58

    C8051T610/1/2/3/4/5/6/7 12. Comparator0 and Comparator1 C8051T610/1/2/3/4/5/6/7 devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 12.1, Comparator1 is shown in Figure 12.2. The two comparators operate identically with the following exceptions: (1) Their input selections differ as ...

  • Page 59

    CP1 + Comparator Input Mux CP1 - CPT1MD Figure 12.2. Comparator1 Functional Block Diagram The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the ...

  • Page 60

    C8051T610/1/2/3/4/5/6/7 CPn+ VIN+ + CPn CPn- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CPnHYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 12.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its ...

  • Page 61

    SFR Definition 12.1. CPT0CN: Comparator0 Control Bit 7 6 CP0EN CP0OUT CP0RIF Name R/W R Type 0 0 Reset SFR Address = 0x9B Bit Name 7 CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. 6 CP0OUT Comparator0 Output ...

  • Page 62

    C8051T610/1/2/3/4/5/6/7 SFR Definition 12.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 Rising-Edge Interrupt ...

  • Page 63

    SFR Definition 12.3. CPT1CN: Comparator1 Control Bit 7 6 CP1EN CP1OUT CP1RIF Name R/W R Type 0 0 Reset SFR Address = 0x9A Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. 6 CP1OUT Comparator1 Output ...

  • Page 64

    C8051T610/1/2/3/4/5/6/7 SFR Definition 12.4. CPT1MD: Comparator1 Mode Selection Bit 7 6 CP1RIE Name R R Type 0 0 Reset SFR Address = 0x9C Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care. 5 CP1RIE Comparator1 Rising-Edge Interrupt ...

  • Page 65

    Comparator Multiplexers C8051T610/1/2/3/4/5/6/7 devices include analog input multiplexers to connect Port I/O pins to the compar- ator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 12.5). The CMX0P1–CMX0P0 bits select the Comparator0 positive input; the ...

  • Page 66

    C8051T610/1/2/3/4/5/6/7 SFR Definition 12.5. CPT0MX: Comparator0 MUX Selection Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x9F Bit Name 7:6 Unused Unused, Read = 00b; Write = Don’t Care 5:4 CMX0N[1:0] Comparator0 Negative Input MUX ...

  • Page 67

    SFR Definition 12.6. CPT1MX: Comparator1 MUX Selection Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x9E Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care 5:4 CMX0N[1:0] Comparator1 Negative Input MUX Selection. ...

  • Page 68

    C8051T610/1/2/3/4/5/6/7 13. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a ...

  • Page 69

    With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time. ...

  • Page 70

    C8051T610/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary Mnemonic Description Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to ...

  • Page 71

    Table 13.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate ...

  • Page 72

    C8051T610/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR ...

  • Page 73

    Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (twos complement) offset relative to the first byte ...

  • Page 74

    C8051T610/1/2/3/4/5/6/7 13.2. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits ...

  • Page 75

    SFR Definition 13.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is ...

  • Page 76

    C8051T610/1/2/3/4/5/6/7 SFR Definition 13.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last arithmetic operation ...

  • Page 77

    Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...

  • Page 78

    C8051T610/1/2/3/4/5/6/7 14.1. Program Memory The CIP-51 core has program memory space. The C8051T610/1/6/7 implements 15872 bytes of this program memory space as in-system, Byte-Programmable EPROM, organized in a contiguous block from addresses 0x0000 to 0x3FFF. Note that ...

  • Page 79

    General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these ...

  • Page 80

    C8051T610/1/2/3/4/5/6/7 SFR Definition 14.1. EMI0CN: External Memory Interface Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xAA Bit Name 7:2 Unused Unused. Read = 000000b; Write = Don’t Care 1:0 PGSEL[1:0] XRAM Page Select. ...

  • Page 81

    Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051T610/1/2/3/4/5/6/7's resources and peripherals. The CIP-51 controller core duplicates the SFRs found ...

  • Page 82

    C8051T610/1/2/3/4/5/6/7 Table 15.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xE0 Accumulator ACC 0xBC ADC0 Configuration ADC0CF 0xE8 ADC0 Control ADC0CN 0xC4 ADC0 Greater-Than Compare High ADC0GTH 0xC3 ADC0 Greater-Than ...

  • Page 83

    Table 15.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xD4 Port 0 Skip P0SKIP 0x90 Port 1 Latch P1 0xF2 Port 1 Input Mode Configuration P1MDIN 0xA5 Port 1 ...

  • Page 84

    C8051T610/1/2/3/4/5/6/7 Table 15.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xC7 Voltage Regulator Control REG0CN 0xEF Reset Source Configuration/Status RSTSRC 0x99 UART0 Data Buffer SBUF0 0x98 UART0 Control SCON0 ...

  • Page 85

    Interrupts The C8051T610/1/2/3/4/5/6/7 includes an extended interrupt system supporting a total of 14 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and exter- nal input pins varies according to the specific version of ...

  • Page 86

    C8051T610/1/2/3/4/5/6/7 16.1. MCU Interrupt Sources and Vectors The C8051T610/1/2/3/4/5/6/7 MCUs support 14 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated ...

  • Page 87

    Table 16.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B RESERVED 0x0043 ...

  • Page 88

    C8051T610/1/2/3/4/5/6/7 SFR Definition 16.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask ...

  • Page 89

    SFR Definition 16.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Unused. Read = 1, Write = Don't Care. 6 PSPI0 Serial Peripheral Interface (SPI0) ...

  • Page 90

    C8051T610/1/2/3/4/5/6/7 SFR Definition 16.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 ECP1 Name R/W R/W Type 0 0 Reset SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit sets the masking of the ...

  • Page 91

    SFR Definition 16.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 PCP1 Name R/W R/W Type 0 0 Reset SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit sets the priority of the ...

  • Page 92

    C8051T610/1/2/3/4/5/6/7 16.3. External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select ...

  • Page 93

    SFR Definition 16.5. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: /INT1 input is active low. 1: /INT1 input is active high. 6:4 ...

  • Page 94

    C8051T610/1/2/3/4/5/6/7 17. EPROM Memory Electrically programmable read-only memory (EPROM) is included on-chip for program code storage. The EPROM memory can be programmed via the C2 debug and programming interface when a special pro- gramming voltage is applied to the V ...

  • Page 95

    EPROM Read Procedure 1. Reset the device using the /RST pin. 2. Wait at least 20 µs before sending the first C2 command. 3. Place the device in core reset: Write 0x04 to the DEVCTL register. 4. Write 0x00 ...

  • Page 96

    C8051T610/1/2/3/4/5/6/7 17.3. Program Memory CRC A CRC engine is included on-chip which provides a means of verifying EPROM contents once the device has been programmed. The CRC engine is available for EPROM verification even if the device is fully read ...

  • Page 97

    Power Management Modes The C8051T610/1/2/3/4/5/6/7 devices have two software programmable power management modes: idle, and stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted, all interrupts and timers ...

  • Page 98

    C8051T610/1/2/3/4/5/6/7 18.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital ...

  • Page 99

    SFR Definition 18.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87 Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software control. 1 STOP Stop Mode ...

  • Page 100

    C8051T610/1/2/3/4/5/6/7 19. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:  CIP-51 halts program execution  Special Function Registers (SFRs) are initialized to ...

  • Page 101

    Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the V ...

  • Page 102

    C8051T610/1/2/3/4/5/6/7 19.2. Power-Fail Reset/V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 19.2). When level above V , ...

  • Page 103

    SFR Definition 19.1. VDM0CN: V Bit 7 6 VDMEN VDDSTAT Name R/W R Type Varies Varies Reset SFR Address = 0xFF Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V tem resets until it is also ...

  • Page 104

    C8051T610/1/2/3/4/5/6/7 19.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on ...

  • Page 105

    SFR Definition 19.2. RSTSRC: Reset Source Bit 7 6 MEMERR C0RSEF Name R R Type 0 Varies Varies Reset SFR Address = 0xEF Bit Name Description 7 Unused Unused. 6 MEMERR EPROM Error Reset Flag. 5 C0RSEF Comparator0 Reset Enable ...

  • Page 106

    C8051T610/1/2/3/4/5/6/7 20. Oscillators and Clock Selection C8051T610/1/2/3/4/5/6/7 devices include a programmable internal high-frequency oscillator and an exter- nal oscillator drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure ...

  • Page 107

    SFR Definition 20.1. CLKSEL: Clock Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xA9 Bit Name 7:1 Unused Unused. Read = 0000000b; Write = Don’t Care 0 CLKSL0 System Clock Source Select Bit. 0: ...

  • Page 108

    C8051T610/1/2/3/4/5/6/7 20.2. Programmable Internal High-Frequency (H-F) Oscillator All C8051T610/1/2/3/4/5/6/7 devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by ...

  • Page 109

    SFR Definition 20.3. OSCICN: Internal H-F Oscillator Control Bit 7 6 IOSCEN IFRDY Name R/W R Type 1 1 Reset SFR Address = 0xB2 Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. 1: Internal ...

  • Page 110

    C8051T610/1/2/3/4/5/6/7 20.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external capacitor or RC network. A CMOS clock may also pro- vide a clock input. In RC, capacitor, or CMOS clock configuration, the clock source should be ...

  • Page 111

    SFR Definition 20.4. OSCXCN: External Oscillator Control Bit 7 6 XOSCMD[2:0] Name R Type 0 0 Reset SFR Address = 0xB1 Bit Name 7 Unused Read = 0b; Write = Don’t Care 6:4 XOSCMD[2:0] External Oscillator Mode Select. 00x: External ...

  • Page 112

    C8051T610/1/2/3/4/5/6/7 20.3.1. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 20.1, “RC Mode”. The capacitor should be no greater than 100 pF; ...

  • Page 113

    Port Input/Output Digital and analog resources are available through 29 I/O pins organized as three byte-wide ports and one 5-bit-wide port on the C8051T610/2/4. The C8051T611/3/5 devices have 25 I/O pins available, organized as three byte-wide ports and one ...

  • Page 114

    C8051T610/1/2/3/4/5/6/7 21.1. Port I/O Modes of Operation Port pins use the Port I/O cell shown in Figure 21.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all ...

  • Page 115

    WEAKPUD (Weak Pull-Up Disable) PxMDOUT.x (1 for push-pull) (0 for open-drain) XBARE (Crossbar Enable) Px.x – Output Logic Value (Port Latch or Crossbar) PxMDIN.x (1 for digital) (0 for analog) To/From Analog Peripheral Px.x – Input Logic Value (Reads 0 ...

  • Page 116

    C8051T610/1/2/3/4/5/6/7 21.2. Assigning Port I/O Pins to Analog and Digital Functions Port I/O pins can be assigned to various analog, digital, and external interrupt functions. The Port pins assigned to analog functions should be configured for analog I/O, and Port ...

  • Page 117

    Assigning Port I/O Pins to INT0 or INT1 external interrupts INT0 and INT1 can be used to trigger an interrupt on any Port 0 I/O pin. These functions do not require dedicated pins, meaning that they can function on ...

  • Page 118

    C8051T610/1/2/3/4/5/6/7 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI ...

  • Page 119

    Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI ...

  • Page 120

    C8051T610/1/2/3/4/5/6/7 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI ...

  • Page 121

    Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). 2. Select the output mode (open-drain or push-pull) for ...

  • Page 122

    C8051T610/1/2/3/4/5/6/7 SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 CP1AE CP1E Name R/W R/W Type 0 0 Reset SFR Address = 0xE1 Bit Name 7 CP1AE Comparator1 Asynchronous Output Enable. 0: Asynchronous CP1 unavailable at Port ...

  • Page 123

    SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE R/W R/W Type 0 0 Reset SFR Address = 0xE2 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for ...

  • Page 124

    C8051T610/1/2/3/4/5/6/7 21.5. Special Function Registers for Accessing and Configuring Port I/O All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the ...

  • Page 125

    SFR Definition 21.4. P0MDIN: Port 0 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF1 Bit Name 7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog mode have their weak pullup, ...

  • Page 126

    C8051T610/1/2/3/4/5/6/7 SFR Definition 21.6. P0SKIP: Port 0 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD4 Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to be skipped by ...

  • Page 127

    SFR Definition 21.8. P1MDIN: Port 1 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF2 Bit Name 7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog mode have their weak pullup, ...

  • Page 128

    C8051T610/1/2/3/4/5/6/7 SFR Definition 21.10. P1SKIP: Port 1 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD5 Bit Name 7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to be skipped by ...

  • Page 129

    SFR Definition 21.12. P2MDIN: Port 2 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF3 Bit Name 7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively). Port pins configured for analog mode have their weak pullup, ...

  • Page 130

    C8051T610/1/2/3/4/5/6/7 SFR Definition 21.14. P2SKIP: Port 2 Skip Bit 7 6 Name R Type 0 0 Reset SFR Address = 0xD6 Bit Name 7:4 Unused Unused. Read = 0000b; Write = Don’t Care. 3:0 P2SKIP[3:0] Port 2 Crossbar Skip Enable ...

  • Page 131

    SFR Definition 21.16. P3MDIN: Port 3 Input Mode Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF4 Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4:0 P3MDIN[4:0] Analog Configuration Bits for P3.4–P3.0 (respectively). ...

  • Page 132

    C8051T610/1/2/3/4/5/6/7 22. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with ...

  • Page 133

    Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version 2.0, ...

  • Page 134

    C8051T610/1/2/3/4/5/6/7 All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE ...

  • Page 135

    When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and ...

  • Page 136

    C8051T610/1/2/3/4/5/6/7 Table 22.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as ...

  • Page 137

    SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 22.2 shows the min- imum setup and hold times for ...

  • Page 138

    C8051T610/1/2/3/4/5/6/7 SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 ENSMB INH Name R/W R/W Type 0 0 Reset SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when set to 1. When ...

  • Page 139

    SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 22.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...

  • Page 140

    C8051T610/1/2/3/4/5/6/7 SFR Definition 22.2. SMB0CN: SMBus Control Bit 7 6 MASTER TXMODE Name R R Type 0 0 Reset SFR Address = 0xC0; Bit-Addressable Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is ...

  • Page 141

    Table 22.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When:  A START is generated. MASTER  START is generated.  SMB0DAT is written before the start of an TXMODE SMBus frame.  A START followed by ...

  • Page 142

    C8051T610/1/2/3/4/5/6/7 22.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...

  • Page 143

    SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...

  • Page 144

    C8051T610/1/2/3/4/5/6/7 22.5.2. Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus ...

  • Page 145

    Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events ...

  • Page 146

    C8051T610/1/2/3/4/5/6/7 22.5.4. Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave ...

  • Page 147

    Table 22.4. SMBus Status Decoding Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK received. 1100 A master data or address byte ...

  • Page 148

    C8051T610/1/2/3/4/5/6/7 Table 22.4. SMBus Status Decoding Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted ...

  • Page 149

    UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “23.1. ...

  • Page 150

    C8051T610/1/2/3/4/5/6/7 23.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...

  • Page 151

    Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 23.3. Figure 23.3. UART Interconnect Diagram 23.2.1. 8-Bit UART ...

  • Page 152

    C8051T610/1/2/3/4/5/6/7 23.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit ...

  • Page 153

    Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it ...

  • Page 154

    C8051T610/1/2/3/4/5/6/7 SFR Definition 23.1. SCON0: Serial Port 0 Control Bit 7 6 Name S0MODE R/W R Type 0 1 Reset SFR Address = 0x98; Bit-Addressable Bit Name 7 S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: ...

  • Page 155

    SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x99 Bit Name 7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB). This SFR accesses two registers; a transmit shift register ...

  • Page 156

    C8051T610/1/2/3/4/5/6/7 Table 23.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Target Baud Rate % Error Baud Rate (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: ...

  • Page 157

    Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple ...

  • Page 158

    C8051T610/1/2/3/4/5/6/7 24.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 24.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...

  • Page 159

    SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data ...

  • Page 160

    C8051T610/1/2/3/4/5/6/7 Master Device Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Master Device GPIO Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection 24.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured ...

  • Page 161

    NSSMD1 (SPI0CN. and NSSMD0 (SPI0CN. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of ...

  • Page 162

    C8051T610/1/2/3/4/5/6/7 SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB NSS (Must Remain High in Multi-Master Mode) Figure 24.5. Master Mode Data/Clock Timing SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB MISO MSB NSS (4-Wire ...

  • Page 163

    SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) 24.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system ...

  • Page 164

    C8051T610/1/2/3/4/5/6/7 SFR Definition 24.1. SPI0CFG: SPI0 Configuration Bit 7 6 SPIBSY MSTEN CKPHA Name R R/W Type 0 0 Reset SFR Address = 0xA1 Bit Name 7 SPIBSY SPI Busy. This bit is set to logic 1 when a SPI ...

  • Page 165

    SFR Definition 24.2. SPI0CN: SPI0 Control Bit 7 6 SPIF WCOL MODF Name R/W R/W Type 0 0 Reset SFR Address = 0xF8; Bit-Addressable Bit Name 7 SPIF SPI0 Interrupt Flag. This bit is set to logic 1 by hardware ...

  • Page 166

    C8051T610/1/2/3/4/5/6/7 SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA2 Bit Name 7:0 SCR[7:0] SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module ...

  • Page 167

    SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 24.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is ...

  • Page 168

    C8051T610/1/2/3/4/5/6/7 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 24.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* ...

  • Page 169

    Table 24.1. SPI Slave Timing Parameters Parameter Description Master Mode Timing (See Figure 24.8 and Figure 24.9) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Shift Edge MIS T SCK Shift Edge to ...

  • Page 170

    C8051T610/1/2/3/4/5/6/7 25. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can ...

  • Page 171

    SFR Definition 25.1. CKCON: Clock Control Bit 7 6 T3MH T3ML T2MH Name R/W R/W Type 0 0 Reset SFR Address = 0x8E Bit Name 7 T3MH Timer 3 High Byte Clock Select. Selects the clock supplied to the Timer ...

  • Page 172

    C8051T610/1/2/3/4/5/6/7 25.1. Timer 0 and Timer 1 Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used ...

  • Page 173

    Pre-scaled Clock SYSCLK T0 GATE0 Crossbar IN0PL XOR /INT0 Figure 25.1. T0 Mode 0 Block Diagram 25.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The ...

  • Page 174

    C8051T610/1/2/3/4/5/6/7 25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the ...

  • Page 175

    Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits in ...

  • Page 176

    C8051T610/1/2/3/4/5/6/7 SFR Definition 25.2. TCON: Timer Control Bit 7 6 TF1 TR1 Name R/W R/W Type 0 0 Reset SFR Address = 0x88; Bit-Addressable Bit Name 7 TF1 Timer 1 Overflow Flag. Set hardware when Timer 1 ...

  • Page 177

    SFR Definition 25.3. TMOD: Timer Mode Bit 7 6 GATE1 C/T1 Name R/W R/W Type 0 0 Reset SFR Address = 0x89 Bit Name 7 GATE1 Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of ...

  • Page 178

    C8051T610/1/2/3/4/5/6/7 SFR Definition 25.4. TL0: Timer 0 Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8A Bit Name 7:0 TL0[7:0] Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer ...

  • Page 179

    SFR Definition 25.6. TH0: Timer 0 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8C Bit Name 7:0 TH0[7:0] Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer 0. ...

  • Page 180

    C8051T610/1/2/3/4/5/6/7 25.2. Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines ...

  • Page 181

    Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 25.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH ...

  • Page 182

    C8051T610/1/2/3/4/5/6/7 SFR Definition 25.8. TMR2CN: Timer 2 Control Bit 7 6 TF2H TF2L TF2LEN Name R/W R/W Type 0 0 Reset SFR Address = 0xC8; Bit-Addressable Bit Name 7 TF2H Timer 2 High Byte Overflow Flag. Set by hardware when ...

  • Page 183

    SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCA Bit Name 7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload ...

  • Page 184

    C8051T610/1/2/3/4/5/6/7 SFR Definition 25.12. TMR2H Timer 2 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCD Bit Name 7:0 TMR2H[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2H register contains the high byte of ...

  • Page 185

    Timer 3 Timer 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the ...

  • Page 186

    C8051T610/1/2/3/4/5/6/7 25.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 25.7. TMR3RLL holds the reload value for TMR3L; ...

  • Page 187

    SFR Definition 25.13. TMR3CN: Timer 3 Control Bit 7 6 TF3H TF3L TF3LEN Name R/W R/W Type 0 0 Reset SFR Address = 0x91; Bit-Addressable Bit Name 7 TF3H Timer 3 High Byte Overflow Flag. Set by hardware when the ...

  • Page 188

    C8051T610/1/2/3/4/5/6/7 SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x92 Bit Name 7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the ...

  • Page 189

    SFR Definition 25.17. TMR3H Timer 3 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x95 Bit Name 7:0 TMR3H[7:0] Timer 3 Low Byte. In 16-bit mode, the TMR3H register contains the high byte of the ...

  • Page 190

    C8051T610/1/2/3/4/5/6/7 26. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. Each capture/compare module ...

  • Page 191

    PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H ...

  • Page 192

    C8051T610/1/2/3/4/5/6/7 26.2. PCA0 Interrupt Sources Figure 26.3 shows a diagram of the PCA interrupt tree. There are six independent event flags that can be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which ...

  • Page 193

    Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high-speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. Each module has Special Function Registers ...

  • Page 194

    C8051T610/1/2/3/4/5/6/7 26.3.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun- ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). ...

  • Page 195

    Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An ...

  • Page 196

    C8051T610/1/2/3/4/5/6/7 26.3.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare ...

  • Page 197

    Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of ...

  • Page 198

    C8051T610/1/2/3/4/5/6/7 26.3.5. 8-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap- ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) ...

  • Page 199

    Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod- ule defines the number of PCA clocks for the low time of the PWM signal. When ...

  • Page 200

    C8051T610/1/2/3/4/5/6/7 26.4. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified ...