AD9516-1/PCBZ Analog Devices Inc, AD9516-1/PCBZ Datasheet

Page 1

... The AD9516-1 is specified for operation over the industrial range of −40°C to +85°C. 1 AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-1 is used, it refers to that specific member of the AD9516 family. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...

Page 2

... Thermal Performance.................................................................... 54   Register Map Overview ................................................................. 55 Register Map Descriptions ............................................................ 59   Applications Information .............................................................. 77   Frequency Planning Using the AD9516.................................. 77   Using the AD9516 Outputs for ADC Clock Applications.... 77   LVPECL Clock Distribution ..................................................... 78   LVDS Clock Distribution .......................................................... 78   CMOS Clock Distribution ........................................................ 79   Outline Dimensions ....................................................................... 80   ...

Page 3

... Changes to Table 56 ........................................................................ 68 Changes to Table 57 ........................................................................ 71 Changes to Table 58 ........................................................................ 73 Changes to Table 59 ........................................................................ 74 Changes to Table 60 and Table 61................................................. 76 Added Frequency Planning Using the AD9516 Section............ 77 Changes to Figure 71 and Figure 73; Added Figure 72.............. 78 Changes to LVPECL Clock Distribution and LVDS Clock Distribution Sections ...................................................................... 78 Updated Outline Dimensions........................................................80 4/07— ...

Page 4

... AD9516-1 SPECIFICATIONS Typical is given for 3.3 V ± 5 S_LVPECL Minimum and maximum values are given over full V POWER SUPPLY REQUIREMENTS Table 1. Parameter S_LVPECL V CP RSET Pin Resistor CPRSET Pin Resistor BYPASS Pin Capacitor PLL CHARACTERISTICS Table 2. Parameter VCO (ON-CHIP) Frequency Range VCO Gain (K ...

Page 5

... Register 0x017[1:0] = 10b; Register 0x018[ Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[ Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[ Register 0x017[1:0] = 10b; Register 0x018[ Rev Page 5.1 kΩ RSET = < V − 0 < V − 0 VCXO/VCO Feedback Divider N— Table 54 AD9516-1 section ) is an approxi- PFD ...

Page 6

... OH OL default amplitude setting with driver not toggling; see Figure 25 for variation over frequency Differential termination 100 Ω at 3.5 mA Differential (OUT, OUT) The AD9516 outputs toggle at higher frequencies, but the output amplitude may not meet the V specification; see Figure − V measurement across a differential pair ...

Page 7

... Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b 1.72 2.31 2.89 ns Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 001100b 5.7 8.0 10.1 ns Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b 0.23 ps/°C −0.02 ps/°C 0.3 ps/°C 0.24 ps/°C Rev Page AD9516-1 − level = 810 LOAD = 10 pF LOAD ...

Page 8

... AD9516-1 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 1 GHz, Output = 1 GHz Divider = Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset At 10 MHz Offset ...

Page 9

... Internal VCO; direct to LVPECL output −46 dBc/Hz −76 dBc/Hz −104 dBc/Hz −123 dBc/Hz −140 dBc/Hz −146 dBc/Hz −47 dBc/Hz −77 dBc/Hz −105 dBc/Hz −124 dBc/Hz −141 dBc/Hz −146 dBc/Hz −54 dBc/Hz −78 dBc/Hz −106 dBc/Hz −125 dBc/Hz −141 dBc/Hz −146 dBc/Hz Rev Page AD9516-1 ...

Page 10

... AD9516-1 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER VCO = 2.46 GHz; LVPECL = 491.52 MHz; PLL LBW = 55 kHz VCO = 2.46 GHz; LVPECL = 122.88 MHz; PLL LBW = 55 kHz VCO = 2.46 GHz; LVPECL = 61.44 MHz; PLL LBW = 55 kHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9 ...

Page 11

... Distribution section only; does not include PLL and VCO; uses rising edge of clock signal 285 fs rms Calculated from SNR of ADC method Distribution section only; does not include PLL and VCO; uses rising edge of clock signal 350 fs rms Calculated from SNR of ADC method Rev Page AD9516-1 ...

Page 12

... AD9516-1 DELAY BLOCK ADDITIVE TIME JITTER Table 13. Parameter 1 DELAY BLOCK ADDITIVE TIME JITTER 100 MHz Output Delay (1600 μA, 0x1C) Fine Adj. 000000 Delay (1600 μA, 0x1C) Fine Adj. 101111 Delay (800 μA, 0x1C) Fine Adj. 000000 Delay (800 μA, 0x1C) Fine Adj. 101111 Delay (800 μ ...

Page 13

... On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor 1.02 MHz Frequency above which the monitor always indicates the presence of the reference 8 kHz Frequency above which the monitor always indicates the presence of the reference 1.6 V 260 mV Rev Page AD9516-1 ...

Page 14

... AD9516-1 POWER DISSIPATION Table 17. Parameter POWER DISSIPATION, CHIP Power-On Default Full Operation; CMOS Outputs at 206 MHz Full Operation; LVDS Outputs at 206 MHz PD Power-Down PD Power-Down, Maximum Sleep V Supply CP POWER DELTAS, INDIVIDUAL FUNCTIONS VCO Divider REFIN (Differential) REF1, REF2 (Single-Ended) VCO PLL Channel Divider ...

Page 15

... TIMING DIAGRAMS t CLK CLK t PECL t LVDS t CMOS Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential t FP Rev Page DIFFERENTIAL 80% LVDS 20 Figure 4. LVDS Timing, Differential SINGLE-ENDED 80% CMOS 10pF LOAD 20 Figure 5. CMOS Timing, Single-Ended Load AD9516-1 ...

Page 16

... AD9516-1 ABSOLUTE MAXIMUM RATINGS Table 18. Parameter VS, VS_LVPECL to GND VCP to GND REFIN, REFIN to GND REFIN to REFIN RSET to GND CPRSET to GND CLK, CLK to GND CLK to CLK SCLK, SDIO, SDO GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, ...

Page 17

... This pin is for bypassing the LDO to ground with a capacitor. CLK Along with CLK, this is the differential input for the clock distribution section. CLK Along with CLK, this is the differential input for the clock distribution section. Rev Page AD9516-1 48 OUT6 (OUT6A) 47 OUT6 (OUT6B) 46 ...

Page 18

... AD9516-1 Input/ Pin No. Output Pin Type 15, 18, 19 3.3 V CMOS 17 I 3.3 V CMOS 21 O 3.3 V CMOS 22 I/O 3.3 V CMOS 23 I 3.3 V CMOS 24 I 3.3 V CMOS 27, 41 Power 37, 44, 59, N/A GND EPAD 56 O LVPECL 55 O LVPECL 53 O LVPECL 52 O LVPECL 43 O LVPECL ...

Page 19

... VOLTAGE ON CP PIN (V) Figure 11. Charge Pump Characteristics at V 5.0 4.5 4.0 3.5 PUMP DOWN PUMP UP 3.0 2.5 2.0 1.5 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) Figure 12. Charge Pump Characteristics at V AD9516-1 2.7 3 4.0 4.5 5 ...

Page 20

... AD9516-1 –140 –145 –150 –155 –160 –165 –170 0.1 1 PFD FREQUENCY (MHz) Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency –210 –212 –214 –216 –218 –220 –222 –224 0 0.5 1.0 1.5 SLEW RATE (V/ns) Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/ REFIN 1 ...

Page 21

... Figure 21. LVDS Output (Differential) at 100 MHz 0.4 0.2 0 –0.2 –0 Figure 22. LVDS Output (Differential) at 800 MHz 2.8 1.8 0.8 –0 2.8 1.8 0.8 –0 Rev Page AD9516 TIME (ns 100 TIME (ns) Figure 23.CMOS Output at 25 MHz TIME (ns) Figure 24. CMOS Output at 250 MHz 1 2 ...

Page 22

... AD9516-1 1600 1400 1200 1000 800 0 1 FREQUENCY (GHz) Figure 25. LVPECL Differential Swing vs. Frequency Using a Differential Probe Across the Output Pair 700 600 500 0 100 200 300 400 500 FREQUENCY (MHz) Figure 26. LVDS Differential Swing vs. Frequency Using a Differential Probe Across the Output Pair ...

Page 23

... Figure 35. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2 –120 –130 –140 –150 –160 –170 10M 100M 10 Figure 36. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20 Rev Page AD9516-1 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 ...

Page 24

... Rev Page 10k 100k 1M 10M FREQUENCY (Hz) OC-48 OBJECTIVE MASK AD9516 F OBJ NOTE: 375UI MAX AT 10Hz OFFSET IS THE MAXIMUM JITTER THAT CAN BE GENERATED BY THE TEST EQUIPMENT. FAILURE POINT IS GREATER THAN 375UI. 0 100 JITTER FREQUENCY (kHz) Figure 41. GR-253 Jitter Tolerance Plot ...

Page 25

... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9516-1 ...

Page 26

... REFIN (REF1) REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9516-1 GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE N DELAY COUNTERS N DIVIDER DIVIDE DIVIDE BY ...

Page 27

... THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9516 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 52 and Table 53 through Table 62). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. High Frequency Clock Distribution—CLK or External VCO > ...

Page 28

... REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9516-1 Figure 43. High Frequency Clock Distribution or External VCO > 1600 MHz GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS PROGRAMMABLE A/B N DELAY COUNTERS N DIVIDER ...

Page 29

... Figure 44. Internal VCO and Clock Distribution Table 24. Settings When Using Internal VCO Register 0x010[1:0] = 00b 0x010 to 0x01E 0x018[0] = 0b, 0x232[ 0x1E0[2:0] 0x1E1[ 0x1E1[ 0x018[0] = 1b, 0x232[ Rev Page AD9516-1 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL ...

Page 30

... REFIN (REF1) REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9516-1 GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE N DELAY COUNTERS N DIVIDER DIVIDE DIVIDE BY ...

Page 31

... Function 0x010[ PFD polarity positive (higher control voltage produces higher frequency) 0x010[ PFD polarity negative (higher control voltage produces lower frequency) After the appropriate register values are programmed, Register 0x232 must be set to 0x01 for the values to take effect. Rev Page AD9516-1 ...

Page 32

... PLL theory and design is helpful. ADIsimCLK™ (V1.2 or later free program that can help with the design and exploration of the capabilities and features of the AD9516, including the design of the PLL loop filter available at www.analog.com/clocks. Phase Frequency Detector (PFD) The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them ...

Page 33

... PUMP Figure 48. Example of External Loop Filter for a PLL Using an External VCO PLL Reference Inputs The AD9516 features a flexible PLL reference input circuit that allows either a fully differential input or two separate single- ended inputs. The input frequency range for the reference inputs is specified in Table 2. Both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals ...

Page 34

... × where the value of P can 16, or 32. Prescaler The prescaler of the AD9516 allows for two modes of operation: a fixed divide (FD) mode and dual modulus (DM) mode where the prescaler divides by P and ( and 3, 4 and 5, 8 and 9, 16 and 17 and 33}. The prescaler modes of operation are given in Table 54, Register 0x016[2:0] ...

Page 35

... VCO frequency is greater than 2400 MHz because the frequency going to the A/B counter is too high. When the AD9516 B counter is bypassed (B = 1), the A counter should be set to 0, and the overall resulting divide is equal to the prescaler setting, P. The possible divide ratios in this mode are 16, and 32 ...

Page 36

... The number of consecutive PFD cycles required for lock is programmable (Register 0x018[6:5]). Analog Lock Detect (ALD) The AD9516 provides an ALD function that can be selected for use at the LD pin. There are two versions of ALD, as follows: • N-channel open-drain lock detect. This signal requires a pull-up resistor to positive supply, VS ...

Page 37

... Holdover The AD9516 PLL has a holdover function. Holdover is implemented by putting the charge pump into a state of high impedance. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. Without this function, the charge pump is placed into a constant pump-up or pump-down state resulting in a massive VCO frequency shift ...

Page 38

... Connect REFMON pin to REFSEL pin. Frequency Status Monitors The AD9516 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 54 ...

Page 39

... VCO CLK CLK VCO Calibration The AD9516 on-chip VCO must be calibrated to ensure proper operation over process and temperature. The VCO calibration is controlled by a calibration controller running off of a divided REFIN clock. The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN clock be present. ...

Page 40

... Internal VCO or External CLK as Clock Source The clock distribution of the AD9516 has two clock input sources: an internal VCO or an external clock connected to the CLK/ CLK pins. Either the internal VCO or CLK must be chosen as the source of the clock signal to distribute ...

Page 41

... When a divider is bypassed 32) × Otherwise This allows (2 to 32) X each channel divider to divide by any integer from 32) × ( × 32) Rev Page AD9516-1 for Divider 0, Divider 1, and Divider 2 X High Cycles N Bypass DCCOFF 0x190[3:0] 0x191[7] 0x192[0] 0x193[3:0] 0x194[7] 0x195[0] 0x196[3:0] ...

Page 42

... AD9516-1 Duty Cycle and Duty-Cycle Correction (0, 1, and 2) The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: • What are the M and N values for the channel? • Is the DCC enabled? • Is the VCO divider used? • ...

Page 43

... X.2 ) for Divider 3, Divider Bypass 3.1 0x199[7:4] 0x199[3:0] 0x19C[4] 3.2 0x19B[7:4] 0x19B[3:0] 0x19C[5] 4.1 0x19E[7:4] 0x19E[3:0] 0x1A1[4] 4.2 0x1A0[7:4] 0x1A0[3:0] 0x1A1 × X.1 X 2). X.2 × D X.1 X.2 AD9516-1 1 DCCOFF 0x19D[0] 0x19D[0] 0x1A2[0] 0x1A2[ × × X.1 X.1 ) can be realized. ...

Page 44

... AD9516-1 Duty Cycle and Duty-Cycle Correction (Divider 3 and Divider 4) The same duty cycle and DCC considerations apply to Divider 3 and Divider Divider 0, Divider 1, and Divider 2 (see the Duty Cycle and Duty-Cycle Correction (0, 1, and 2) section); however, with these channel dividers, the number of possible configurations is even more complex ...

Page 45

... X.1 50% Case 4 When Φ 50% Δt = 50% (Φ X.1 Fine Delay Adjust (Divider 3 and Divider 4) 50% Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes 50% an analog delay element that can be programmed to give variable time delays (Δt) in the clock signal at that output. ( X.1 X.2 X.1 ...

Page 46

... VCO divider) and an uncertainty one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9516. The delay from the output clocking is between 14 and 15 cycles of clock at the channel divider input, plus either one cycle of the VCO divider ...

Page 47

... SYNC operation. Between outputs and after synchronization, this allows for the setting of phase offsets. The AD9516 outputs are in pairs, sharing a channel divider per pair (two pairs of pairs, four outputs, in the case of CMOS). The synchronization conditions apply to both outputs of a pair. ...

Page 48

... CMOS Output B. However, when CMOS Output A is powered up, CMOS Output B can be powered on or off separately. OUT OUT RESET MODES The AD9516 has several ways to force the chip into a reset condition that restores all registers to their default values and makes these settings active. Power-On Reset—Start-Up Conditions When V Applied A power-on reset (POR) is issued when the V turned on ...

Page 49

... LVPECL output circuitry from damage that could be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. When the AD9516 power-down, the chip is in the following state: • The PLL is off (asynchronous power-down). • ...

Page 50

... PORT SDIO 22 Figure 62. Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT A write or a read operation to the AD9516 is initiated by pulling CS low. CS stall high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (see CS can temporarily return high on any byte ...

Page 51

... The default mode of the AD9516 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin also possible to set the AD9516 to unidirectional mode via the SDO active bit (Register 0x000[0] = 1b). In unidirectional mode, the readback data appears on the SDO pin. ...

Page 52

... AD9516-1 Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 R A12 = 0 CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 64. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data ...

Page 53

... Setup time between SCLK rising edge and CS rising edge (end of communication cycle Minimum period that SCLK should logic high state HIGH t Minimum period that SCLK should logic low state LOW t SCLK to valid SDIO and SDO (see Figure 67 CLK Figure 69. Serial Control Port Timing—Write Rev Page AD9516 ...

Page 54

... Junction-to-case thermal resistance (die-to-heat sink) per MIL-STD-883, Method 1012.1 JC Ψ Junction-to-top-of-package characterization parameter, natural convection per JEDEC JESD51-2 (still air) JT The AD9516 is specified for a case temperature (T that T is not exceeded, an airflow source can be used. CASE Use the following equation to determine the junction ...

Page 55

... REF1 Differential power-on power-on reference Holdover External Holdover enable holdover enable control REF2 REF1 Digital frequency > frequency > lock detect threshold threshold AD9516-1 Default Value (Hex) 0x18 0x01 0x00 0x7D 0x01 0x00 0x00 0x03 0x00 0x06 0x00 0x06 0x00 0x00 0x00 0x00 ...

Page 56

... AD9516-1 Reg. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 Fine Delay Adjust—OUT6 to OUT9 0x0A0 OUT6 delay bypass 0x0A1 OUT6 delay Blank full-scale 0x0A2 OUT6 delay Blank fraction 0x0A3 OUT7 delay bypass 0x0A4 OUT7 delay Blank full-scale 0x0A5 OUT7 delay Blank fraction ...

Page 57

... Reserved Reserved Blank Blank Reserved Power- Power-down down VCO clock clock input interface section Blank Rev Page AD9516-1 Bit 2 Bit 1 Bit 0 (LSB) Divider 0 high cycles Divider 0 phase offset Divider 0 Divider 0 direct to DCCOFF output Divider 1 high cycles Divider 1 phase offset Divider 1 Divider 1 ...

Page 58

... AD9516-1 Reg. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 System 0x230 Power-down and sync 0x231 Update All Registers 0x232 Update all registers Bit 5 Bit 4 Bit 3 Reserved Blank Blank Rev Page Bit 2 Bit 1 Bit 0 (LSB) Power- Power- Soft sync down sync down distribution ...

Page 59

... Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default). 1: SDO used for read, SDIO used for write; unidirectional mode. Uniquely identifies the dash version (-0 through -4) of the AD9516. AD9516-0: 0x01. AD9516-1: 0x41. ...

Page 60

... AD9516-1 Table 54. PLL Reg. Addr. (Hex) Bits Name Description 0x010 7 PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity; Bit positive; higher control voltage produces higher frequency (default). 1: negative; higher control voltage produces lower frequency. ...

Page 61

... AND (status of selected reference) AND (status of VCO LVL Status of VCO frequency (active low LVL Selected reference (low = REF2, high = REF1 LVL Digital lock detect (DLD) (active low LVL Holdover active (active low LVL LD pin comparator output (active low). Rev Page AD9516 ...

Page 62

... AD9516-1 Reg. Addr. (Hex) Bits Name Description 0x017 [1:0] Antibacklash 1 pulse width 0x018 [6:5] Lock detect Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked counter condition Digital lock detect If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock window detect flag is set ...

Page 63

... AND (status of selected reference) AND (status of VCO LVL Status of VCO frequency (active low LVL Selected reference (low = REF2, high = REF1 LVL Digital lock detect (DLD); active low LVL Holdover active (active low LVL Not available. Do not use. Rev Page AD9516-1 ...

Page 64

... AD9516-1 Reg. Addr. (Hex) Bits Name Description 0x01B [4:0] REFMON Selects the signal that is connected to the REFMON pin. pin control 0x01C 7 Disable Disables or enables the switchover deglitch circuit. switchover 0: enables switchover deglitch circuit (default). deglitch 1: disables switchover deglitch circuit. 6 Select REF2 If Register 0x01C, Bit select reference for PLL ...

Page 65

... Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency threshold set by Register 0x01A, Bit 6. 0: REF1 frequency is less than threshold frequency. 1: REF1 frequency is greater than threshold frequency. 0 Digital lock detect Read-only register. Digital lock detect. 0: PLL is not locked. 1: PLL is locked. Rev Page AD9516-1 ...

Page 66

... AD9516-1 Table 55. Fine Delay Adjust—OUT6 to OUT9 Reg. Addr. (Hex) Bits Name 0x0A0 0 OUT6 delay bypass 0x0A1 [5:3] OUT6 ramp capacitors [2:0] OUT6 ramp current 0x0A2 [5:0] OUT6 delay fraction 0x0A3 0 OUT7 delay bypass 0x0A4 [5:3] OUT7 ramp capacitors Description Bypasses or uses the delay function. ...

Page 67

... Current (μ 200 (default 400 600 800 1000 1200 1400 1600 Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000 gives zero delay. Only delay values decimals (101111b; 0x2F) are supported (default = 0x00). Rev Page AD9516-1 ...

Page 68

... AD9516-1 Reg. Addr. (Hex) Bits Name 0x0A9 0 OUT9 delay bypass 0x0AA [5:3] OUT9 ramp capacitors [2:0] OUT9 ramp current 0x0AB [5:0] OUT9 delay fraction Table 56. LVPECL Outputs Reg. Addr. (Hex) Bits Name 0x0F0 4 OUT0 invert [3:2] OUT0 LVPECL differential voltage [1:0] ...

Page 69

... Normal operation Partial power-down, reference on; use only if there are no external load resistors Partial power-down, reference on, safe LVPECL power-down (default Total power-down, reference off; use only if there are no external load resistors. Rev Page AD9516 Output On Off Off Off Output On Off Off ...

Page 70

... AD9516-1 Reg. Addr. (Hex) Bits Name 0x0F4 4 OUT4 invert [3:2] OUT4 LVPECL differential voltage [1:0] OUT4 power-down 0x0F5 4 OUT5 invert [3:2] OUT5 LVPECL differential voltage [1:0] OUT5 power-down Description Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (V ...

Page 71

... LVDS (default). 1: CMOS. Sets output current level in LVDS mode. This has no effect in CMOS mode Current ( Rev Page AD9516-1 OUT4B (CMOS) OUT4 (LVDS) Inverting Noninverting Noninverting Noninverting (default) Inverting Noninverting Noninverting Noninverting Noninverting Inverting Inverting Inverting Noninverting Inverting Inverting Inverting Recommended Termination (Ω ...

Page 72

... AD9516-1 Reg. Addr. (Hex) Bits Name 0x141 0 OUT7 power-down 0x142 [7:5] OUT8 output polarity 4 OUT8 CMOS B 3 OUT8 select LVDS/CMOS [2:1] OUT8 LVDS output current 0 OUT8 power-down 0x143 [7:5] OUT9 output polarity 4 OUT9 CMOS B 3 OUT9 select LVDS/CMOS Description Power-down output (LVDS/CMOS). ...

Page 73

... Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. Forces divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. Rev Page AD9516-1 Recommended Termination (Ω) 100 100 (default ...

Page 74

... AD9516-1 Reg. Addr. (Hex) Bits Name 0x194 4 Divider 1 start high [3:0] Divider 1 phase offset 0x195 1 Divider 1 direct to output 0 Divider 1 DCCOFF 0x196 [7:4] Divider 2 low cycles [3:0] Divider 2 high cycles 0x197 7 Divider 2 bypass 6 Divider 2 nosync 5 Divider 2 force high 4 Divider 2 start high [3:0] ...

Page 75

... Forces Divider 4 output high. Requires that nosync also be set. 0: forces low (default). 1: forces high. Divider 4.2 starts high/low. 0: starts low (default). 1: starts high. Divider 4.1 starts high/low. 0: starts low (default). 1: starts high. Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Rev Page AD9516-1 ...

Page 76

... AD9516-1 Table 60. VCO Divider and CLK Input Reg. Addr (Hex) Bits Name 0x1E0 [2:0] VCO divider 0x1E1 4 Power down clock input section 3 Power down VCO clock interface 2 Power down VCO and CLK 0x1E1 1 Select VCO or CLK 0 Bypass VCO divider Table 61. System Reg ...

Page 77

... MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.45 GHz to 2.95 GHz) of the AD9516 family. If the desired frequency plan can be achieved with a version of the AD9516 that has a lower VCO frequency, choosing the lower frequency part results in the lowest phase noise and the lowest jitter ...

Page 78

... Thevenin-equivalent termination uses a resistor network to provide 50 Ω termination voltage that is below V − 1.3 V). S driver. In this case, VS_LVPECL on the AD9516 should equal V of the receiving buffer. Although the resistor combination shown in Figure 72 results bias point of VS_LVPECL − the V S 127Ω ...

Page 79

... Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9516 offers both LVPECL and LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters ...

Page 80

... PLANE ORDERING GUIDE 1 Model Temperature Range AD9516-1BCPZ −40°C to +85°C AD9516-1BCPZ-REEL7 −40°C to +85°C AD9516-1/PCBZ RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 9.00 BSC SQ 0.60 MAX 48 0 ...