STEVAL-ILB008V1 STMicroelectronics, STEVAL-ILB008V1 Datasheet - Page 16

BOARD EVAL BALLAST FOR L6585DE

STEVAL-ILB008V1

Manufacturer Part Number
STEVAL-ILB008V1
Description
BOARD EVAL BALLAST FOR L6585DE
Manufacturer
STMicroelectronics
Type
Power Factor Correctionr

Specifications of STEVAL-ILB008V1

Main Purpose
Lighting, Ballast Control
Embedded
No
Utilized Ic / Part
L6585DE
Primary Attributes
4 x 18w, T8 Lamps
Secondary Attributes
Preheating Ignition
Input Voltage
90 V to 265 V
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
L6585DE
Other names
497-10544
Application information
5.2.2
5.2.3
16/33
The ZCD input can be connected directly to an auxiliary winding of the PFC choke in order
to turn on the MOSFET when the choke current reaches zero. This pin has internal clamps
and high current capability that makes it compliant with a very wide range of input voltage.
At startup, when PFC choke is not yet energized, an internal starter gives ZCD pulses to the
PFC gate driver with a repetition rate of approximately 15 kHz.
By turning off the MOSFET when the current reaches the threshold and turning on the
MOSFET when the choke current reaches zero, a triangular input current whose peaks are
modulated by the MULT voltage is obtained. By feeding the MULT pin with the mains
waveform, a power factor correction and THD reduction is achieved.
Leading edge blanking
Usually current sense voltage is filtered by means of an RC network in order to avoid false
turning off of the MOSFET because of the discharge current related to parasitic drain
capacitance present at the beginning of the on time of the MOSFET. This filtering generates
a delay between the actual threshold crossing and the input triggering. During this time the
PFC inductor current increases and the choke may saturate. A leading edge blanking
structure makes the PFCCS input active only after 200 ns (typ.) after the PFG turn on. This
allows the use of inductors with lower saturation current. However, if saturation occurs, a
choke saturation protection turns off the PFC gate as soon as the voltage at pin PFCCS is
above 1.7 V.
Figure 6.
THD optimizer feature
When the input voltage passes through zero, the PFC choke cannot store energy because
of the very low voltage across it. This may cause heavy crossover distortion and subsequent
THD degradation. A small offset voltage superimposed over the MULT voltage can reduce
this issue.
The internal THD optimizer increases the performance when the mains voltage reaches
zero; this reduces crossover distortion and avoids offset introduction.
PFCCS waveforms
L6585DE

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