STEVAL-PCC010V1

Manufacturer Part NumberSTEVAL-PCC010V1
DescriptionBOARD EVAL FOR ST802RT1
ManufacturerSTMicroelectronics
STEVAL-PCC010V1 datasheets
 

Specifications of STEVAL-PCC010V1

Main PurposeInterface, Ethernet Controller (PHY and MAC)EmbeddedYes, MCU, 8-Bit
Utilized Ic / PartST802RT1Primary Attributes1 Port, 100BASE-TX/10BASE-T
Secondary AttributesMII, RMIILead Free Status / RoHS StatusLead free / RoHS Compliant
Other names497-10360  
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Features
IEEE802.3 10Base-T and IEEE802.3u
100Base-TX, 100Base-FX (ST802RT1B only)
transceiver
Support for IEEE802.3x flow control
Provides full-duplex operation in both 100
Mbps and 10 Mbps modes
Register bit strap during HW reset
Auto MDI-X for 10/100 Mb/s
Auto-negotiation
Provides loop-back mode for diagnostics
Programmable LED display for operating mode
and functionality signaling
MII / RMII interface
MDC / MDIO serial management interface
Optimized deterministic latency for real-time
Ethernet operation
Supports external transformer with turn ratio
1.414:1 on Tx/Rx side
Self-termination transceiver for external
components and power saving
Operation from single 3.3 V supply
High ESD tolerance
48-pin LQFP 7 x 7 package
Extended temp. range: -40 °C to +105 °C
Power dissipation < 315 mW (typ)
Applications
Industrial control
Factory automation
High-end peripherals
Table 1.
Device summary
Order codes
ST802RT1AFR
ST802RT1BFR
February 2010
10/100 real-time Ethernet 3.3 V transceiver
Building automation
Telecom infrastructure
Description
The ST802RT1x is a high-performance fast
Ethernet physical layer interface for 10Base-T,
100Base-TX and 100Base-FX applications. It is
designed using advanced CMOS technology to
provide MII and RMII interfaces for easy
attachment to 10/100 media access controllers
(MAC). The ST802RT1x supports the 100Base-
TX of IEEE802.3u and 10Base-T of IEEE802.3i
and 100Base FX of IEEE 802.3u (B version only).
The ST802RT1x supports both half-duplex and
full-duplex operation at 10 and 100 Mbps
operation. Its operating mode can be set using
auto-negotiation, parallel detection or manual
control. It allows for the support of auto-
negotiation functions for speed and duplex
detection. The automatic MDI / MDIX feature
compensates for the use of a crossover cable.
With auto MDIX, the ST802RT1x automatically
detects what is on the other end of the network
cable and switches the TX & RX pin functionality
accordingly.
Temperature range
- 40 to 105 °C
- 40 to 105 °C
Doc ID 17049 Rev 1
ST802RT1A
ST802RT1B
LQFP48
Package
LQFP48
LQFP48
1/58
www.st.com
58

STEVAL-PCC010V1 Summary of contents

  • Page 1

    Features ■ IEEE802.3 10Base-T and IEEE802.3u 100Base-TX, 100Base-FX (ST802RT1B only) transceiver ■ Support for IEEE802.3x flow control ■ Provides full-duplex operation in both 100 Mbps and 10 Mbps modes ■ Register bit strap during HW reset ■ Auto MDI-X for ...

  • Page 2

    Contents Contents 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    ST802RT1A, ST802RT1B 7.16 Automatic MDI / MDIX feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    ST802RT1A, ST802RT1B List of figures Figure 1. ST802RT1x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    Features 1 Features 1.1 Physical layer ● The ST802RT1x integrates the entire physical layer functions of 100Base-TX, 10Base- T and 100Base-FX (B version only) ● Optimized deterministic latency for real-time Ethernet operation ● Provides full-duplex operation in both 100 Mbps ...

  • Page 7

    ST802RT1A, ST802RT1B 2 Device block diagram Figure 1. ST802RT1x block diagram 10BASE-T 10BASE-T 100BASE-TX 100BASE-TX 100BASE-FX 100BASE-FX TX CHANNEL TX CHANNEL TRANSMITTER TRANSMITTER HW HW CONFIG CONFIG HW PROG PINS HW PROG PINS Serial management Serial management MII/RMII INTERFACES MII/RMII ...

  • Page 8

    System and block diagrams 3 System and block diagrams Figure 2. System diagram of the ST802RT1A/B Figure 3. System diagram of the ST802RT1B in FX mode 8/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...

  • Page 9

    ST802RT1A, ST802RT1B 4 Pin configuration Figure 4. Pin configuration - ST802RT1A TX_CLK/LPBK_EN TX_CLK/LPBK_EN TX_EN TX_EN GNDA GNDA ...

  • Page 10

    Pin configuration Figure 5. Pin configuration - ST802RT1B TX_CLK/LPBK_EN TX_CLK/LPBK_EN TX_EN TX_EN GNDA GNDA ...

  • Page 11

    ST802RT1A, ST802RT1B 5 Pin description Table 2. Pin description of the ST802RT1x Pin n° Name ST802RT1x 1 TX_CLK/LPBK_EN 2 TX_EN 3 GNDA 4 VCCA 5 TXD0 6 TXD1 7 TXD2/SCLK 8 TXD3/MII_CFG1 9 PWRDWN/MDINT 10 RESERVED 11 RESERVED 12 GND ...

  • Page 12

    Pin description Table 2. Pin description of the ST802RT1x (continued) Pin n° Name ST802RT1x 32 OVDD 33 GND DVDD 37 RX_CLK 38 RXDV/MII_CFG0 39 CRS_TXD4 40 RXER_RXD4 41 DVDD 42 RXD3/PHYADDR4 43 RXD2/PHYADDR3 44 RXD1/PHYADDR2 ...

  • Page 13

    ST802RT1A, ST802RT1B Table 4. Pin functions of the ST802RT1x Pin n° Name Type Data interface 5 TXD0 6 TXD1 I 7 TXD2 8 TXD3 7 SCLK I 2 TX_EN TX_CLK RXER O 42 RXD3 ...

  • Page 14

    Pin description Table 4. Pin functions of the ST802RT1x (continued) Pin n° Name Type TXP I/O 18 TXN 25 SDP I 48 SDN 15 RXP I/O 14 RXN 21 IREF O 28 LED_LINK ...

  • Page 15

    ST802RT1A, ST802RT1B Table 4. Pin functions of the ST802RT1x (continued) Pin n° Name Type 3, 16, 19, 20, GNDA Ground Analog ground 23 Strap pins The ST802RT1x uses many of the functional pins as strap options. The values of these ...

  • Page 16

    Pin description Table 5. Signal detect SDN Ground Ground Voltage > 0.6 V PECL (PECL ) LOW MID PECL HIGH (PECL ) MID PECL HIGH PECL LOW (PECL ) MID Table 6. MII_CFG0, MII_CFG1 configuration MII mode RMII mode Reserved ...

  • Page 17

    ST802RT1A, ST802RT1B 6 Registers and descriptors description All of the management data control and status registers in the ST802RT1x's register set are accessed via a Write or Read operation on the serial MDIO port. This access requires a protocol described ...

  • Page 18

    Registers and descriptors description 6.2 Register description Table 9. Abbreviations Legend STRAP LH LL Table 10. RN00 [0d00, 0x00]: Control register Bit Bit name 1 -> software reset, reset in process 0 -> normal operation 15 ...

  • Page 19

    ST802RT1A, ST802RT1B Table 10. RN00 [0d00, 0x00]: Control register (continued) Bit Bit name 1 -> Collision test enabled 7 Collision test 0 -> Normal operation Active only in loop-back mode (RN00[14]=1) 6 RESERVED Not used 5 RESERVED Not used 4 ...

  • Page 20

    Registers and descriptors description be cleared by writing a “0” to bit 10 of the control register resetting the chip. When this bit is read, it returns a “1” when the chip is in isolate mode; otherwise it ...

  • Page 21

    ST802RT1A, ST802RT1B Table 11. RN01 [0d01, 0x01]: Status register Bit Bit name 100BASE-T4 0 -> PHY not able to perform 100BASE-T4 15 ABILITY Fixed to 0 100BASE-X 1 -> PHY able to perform full-duplex 100BASE-X 14 Full Duplex Fixed to ...

  • Page 22

    Registers and descriptors description Reserved bits: Ignore ST802RT1x output when these bits are read. Preamble suppression: This bit is a read-only bit and can be set by bit 1 of the RN14 register. When read as a logic “1”, the ...

  • Page 23

    ST802RT1A, ST802RT1B Table 14. RN04 [0d04, 0x04]: Auto-negotiation advertisement register Bit Bit name 1 -> Next page transfer supported 15 Next Page 0 -> Next page transfer not supported 14 RESERVED --- 1 -> Advertises that this device has detected ...

  • Page 24

    Registers and descriptors description suppressed from transmission. Resetting the chip restores the default bit values. Reading the register returns the values last written to the corresponding bits, or else the default values if no write has been completed since the ...

  • Page 25

    ST802RT1A, ST802RT1B Reserved: Ignore when read. LP pause: Indicates that the link partner pause bit is set. LP selector field: Bits 4:0 of the link partner ability register reflect the value of the Link partner's selector field. These bits are ...

  • Page 26

    Registers and descriptors description Table 17. RN07 [0d07, 0x07]: Auto-negotiation next page transmit register Bit Bit name 1 -> additional next page(s) will follow 15 Next Page 0 -> last page 14 RESERVED -- 1 -> Message page transmitting 13 ...

  • Page 27

    ST802RT1A, ST802RT1B Next page: Indicates whether this is the last next page. Msg page: Differentiates a message page from an unformatted page. Ack2: Indicates that link partner has the ability to comply with the message. Toggle: Used by the arbitration ...

  • Page 28

    Registers and descriptors description Table 20. RN11 [0d17, 0x11]: Receiver configuration information and interrupt status register Bit Bit name 15:11 RESERVED --- 1 -> FX mode set 0 -> FX mode not set 10 FX_MODE If set to '1', auto-negotiation ...

  • Page 29

    ST802RT1A, ST802RT1B Table 21. RN12 [0d18, 0x12]: Receiver event interrupts register Bit Bit name 15:9 RESERVED NOT USED INTERRUPT OUTPUT ENABLE: 8 INT_OE_N 1 -> PWRDWN/MDINT is a power-down input 0 -> PWRDWN/MDINT is an interrupt output INTERRUPT ENABLE: 7 ...

  • Page 30

    Registers and descriptors description Table 22. RN13 [0d19, 0x13]: 100Base-TX control register Bit Bit name 15:14 RESERVED -- Disable RX err 1 -> RX error counter disabled 13 counter 0 -> Normal operation 1 -> Auto-negotiation complete 12 Auto Neg ...

  • Page 31

    ST802RT1A, ST802RT1B Table 24. RN18 [0d24, 0x18]: Auxiliary control register Bit Bit name 1 -> Disables jabber detection (10BaseT) 15 Jabber disable 0 -> Normal operation 14 RESERVED -- 13:8 RESERVED -- 7:5 RESERVED -- MDIO Power 1 -> Stops ...

  • Page 32

    Registers and descriptors description Table 25. RN19 [0d25, 0x19]: Auxiliary status register (continued) Bit Bit name 1 -> A fault has been detected via the parallel detection Parallel Detection 7 function (updated on read) Fault 0 -> A fault has ...

  • Page 33

    ST802RT1A, ST802RT1B Table 26. RN1B [0d27, 0x1B]: Auxiliary mode 2 register Bit Bit name 15:12 RESERVED -- 11:10 RESERVED -- 1 -> led_link pad: ON for link_up, BLINK for activity led_speed pad: ON for 100 Mb, OFF for 10 Mb ...

  • Page 34

    Registers and descriptors description Table 27. RN1C [0d28, 0x1C]: 10Base-T error and general status register Bit Bit name 15:14 RESERVED --- 1 -> MDI-X configuration used 13 MDIX Status 0 -> MDI configuration used 1 -> MDIX force (if not ...

  • Page 35

    ST802RT1A, ST802RT1B Table 28. RN1E [0d30, 0x1E]: Auxiliary PHY register Bit Bit name 1 -> AN 100Base-TX full-duplex selected 15 HCD 100base-Tx FDX 0 -> AN 100Base-TX full-duplex not selected 1 -> AN 100Base-T4 selected (not supported) 0 -> AN ...

  • Page 36

    Registers and descriptors description HCD 10BaseT: Bits 15:11 of the auxiliary PHY register are five read-only bits that report the highest common denominator (HCD) result of the auto-negotiation process. Immediately upon entering the link pass state after each reset or ...

  • Page 37

    ST802RT1A, ST802RT1B Table 30. RS1B [0d27, 0x1B]: Misc status/error/test shadow register Bit Bit name 1 -> MLT3 enabled with no errors (TX100 only) 15 MLT3 Detect 0 -> MLT3 disabled or MLT3 error TX100 CABLE LENGTH (m): 000 <= 20 ...

  • Page 38

    Device operation 7 Device operation The ST802RT1x includes a 10/100 Base-T Ethernet transceiver with MII, RMII interfaces for data and control from/to the station management entity (STE). The ST802RT1x integrates the IEEE802.3u compliant functions of PCS (physical coding sub-layer), PMA ...

  • Page 39

    ST802RT1A, ST802RT1B Wave-shaper and media signal driver: In order to reduce the energy of the harmonic frequency of transmission signals, the device provides the wave-shaper prior to the line driver to smooth out, but maintain symmetric, the rising/falling edge of ...

  • Page 40

    Device operation 7.3 10Base-T transmit operation In 10Base-T, the device's TX channel includes the parallel-to-serial converter, NRZ to manchester encoder, link pulse generation, and an internal physical ethernet wire interface (Phy). It also provides collision detection and SQE test for ...

  • Page 41

    ST802RT1A, ST802RT1B Auto-negotiation exchanges information with the network partner using the fast link pulses (FLPs burst of link pulses. FLP’s contain 16 bits of signaling information to advertise all supported capabilities, determined by register RN04 (auto-negotiation advertisement register), ...

  • Page 42

    Device operation Write 0180h to RN12 to set INT_EN and INT_OE_N; Write 0010h to RN12 to set LK_DWN_EN; Monitor PWRDWN/MDINT. When the PWRDWN/MDINT pin asserts low, the user should read the RN11 register to see if the LK_DWN is set, ...

  • Page 43

    ST802RT1A, ST802RT1B 7.12 Reset operation There are two ways to reset the ST802RT1x. Hardware reset: the ST802RT1x can be reset via the RESET pin (pin 29). The active low reset input signal is required for at least 1 ms, and ...

  • Page 44

    Device operation 7.15 Transmit isolation Figure 7. Transmit isolation Transmit isolation isolates the PHY from the MII and Tx +/- interface and is activated by setting bit 5 of the 100Base-TX control register (RN13[5]). As with isolate mode, all MII ...

  • Page 45

    ST802RT1A, ST802RT1B 7.18 FX mode operation Each port of the ST802RT1x may also be configured for 100BASE-FX transmission over fiber optics via a pseudo-ECL (PECL) interface. In 100Base-Fx mode, scrambling and MLT3-to-binary conversion are bypassed when transmitting, whereas in reception ...

  • Page 46

    Device operation These two signals can be either driven by standard CMOS levels or by PECL levels. The data coming from the optical transceiver are PECL signals and need to be converted to CMOS level before being delivered to the ...

  • Page 47

    ST802RT1A, ST802RT1B Figure 9. Implementation of the PECL TX section 7.21 PECL receiver The data signals coming from the optical transceiver are in PECL format and need to be converted to CMOS level before being transmitted to the data and ...

  • Page 48

    Device operation 7.22 Far-end-fault For 100Base-FX mode (which does not support auto-negotiation), the ST802RT1x implements the IEEE 802.3 standard far-end-fault mechanism for the indication and detection of remote error conditions. If the far-end-fault is enabled, a PHY transmits the far- ...

  • Page 49

    ST802RT1A, ST802RT1B 8 Electrical specifications and timings Table 34. Absolute maximum ratings Parameter Supply voltage ( Input voltage Output voltage Storage temperature Ambient temperature ESD protection Note: Absolute maximum ratings are those values beyond which damage to the ...

  • Page 50

    Electrical specifications and timings Table 35. General DC specification (continued) Symbol Parameter XTAL conditions t X1 duty cycle X1d t X1 frequency X1f t X1 tolerance X1t t X1 load capacitance X1CL 10Base-T normal link pulse (NLP) Tnps NLP start ...

  • Page 51

    ST802RT1A, ST802RT1B Figure 11. Normal link pulse timings Figure 12. Fast link pulse timing Electrical specifications and timings Doc ID 17049 Rev 1 51/58 ...

  • Page 52

    Electrical specifications and timings Figure 13. MII management clock timing 52/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...

  • Page 53

    ST802RT1A, ST802RT1B 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ...

  • Page 54

    Package mechanical data Table 36. LQFP48 mechanical data Dim 54/58 mm Min. Typ. 0.05 1.35 1.4 0.17 0.22 0.09 8.80 9 6.80 7 5.50 8.80 ...

  • Page 55

    ST802RT1A, ST802RT1B Figure 14. Dimensions of the LQFP48 package Doc ID 17049 Rev 1 Package mechanical data 0110596 55/58 ...

  • Page 56

    Package mechanical data Figure 15. LQFP48 footprint recommended data (mm.) 56/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...

  • Page 57

    ST802RT1A, ST802RT1B 10 Revision history Table 37. Document revision history Date Revision 02-Feb-2010 1 Initial release. Doc ID 17049 Rev 1 Revision history Changes 57/58 ...

  • Page 58

    ... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...