STEVAL-PCC010V1 STMicroelectronics, STEVAL-PCC010V1 Datasheet - Page 36

• Manufacturer Part Number: STEVAL-PCC010V1
• Description: BOARD EVAL FOR ST802RT1
• Manufacturer: STMicroelectronics

Specifications of STEVAL-PCC010V1

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST802RT1
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: MII, RMII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10360

Registers and descriptors description
Table 29.
36/58
15:8
Bit
6:0
7
Registers Enable
RESERVED
RESERVED
Bit name
Shadow
HCD 10BaseT: Bits 15:11 of the auxiliary PHY register are five read-only bits that report the
highest common denominator (HCD) result of the auto-negotiation process. Immediately
upon entering the link pass state after each reset or restart auto-negotiation, only one of
these five bits will be a “1”. The link pass state is identified by a “1” in bit 6 or 7 of this
register. The HCD bits are reset to “0” every time auto-negotiation is restarted or the
ST802RT1x is reset. Note that for their intended application, these bits uniquely identify the
HCD only after the first link pass after reset or restart of auto-negotiation. On later link fault
and subsequent re-negotiations, if the ability of the link partner is different, more than one of
the above bits may be active. These bits are only set for full auto-negotiation handshake,
and not for parallel detection of forced speed modes. Note that bit 14, HCD_T4, is never set
in the ST802RT1x.
Reserved: Ignore when read.
Restart auto-negotiation: A self-clearing bit that allows the auto-negotiation process to be
restarted, regardless of the current status of the state machine. For this bit to work, auto-
negotiation must be enabled. Writing a “1” to this bit restarts auto-negotiation. Since the bit
is self-clearing, it always returns a “0” when read. The operation of this bit is identical to bit 9
of the control register.
Auto-negotiation complete: This read-only bit returns a “1” after the auto-negotiation
process has been completed. It remains “1” until the auto-negotiation is restarted, a link fault
occurs, or the chip is reset. If auto-negotiation is disabled, or the process is still in progress,
the bit returns a “0”.
Auto-negotiation ack: This read-only bit is set to “1” when the arbitrator state machine
exits the acknowledged detect state. It remains high until the auto-negotiation process is
restarted, or the ST802RT1x is reset.
Auto-negotiation ability: This read-only bit returns a “1” when the auto-negotiation state
machine is in the ability detect state. It enters this state a specified time period after the
auto-negotiation process begins, and exits after the first FLP burst or link pulses are
detected from the link partner. This bit returns a “0” any time the auto-negotiation state
machine is not in the ability detect state.
Super isolate: Writing a “1” to this bit places the ST802RT1x into the super isolate mode.
Similar to the isolate mode, all MII inputs are ignored, and all MII outputs are tri-stated.
Additionally, all link pulses are suppressed. This allows the ST802RT1x to coexist with
another PHY on the same adapter card, with only one being activated at any time.
RN1F [0d31, 0x1F]: Shadow registers enable register
NOT USED
1 -> Shadow registers enabled
0 -> Normal operation
When this bit is set, registers at addresses 1B are masked
by correspondent shadow registers
Self-clearing functionality added to this bit when shadow
registers are enabled
Not used
Doc ID 17049 Rev 1
Description
ST802RT1A, ST802RT1B
00000000b
0000000b
Default
0
Type
RW
RW
RO
RO
Type
SC