DS50PCI402EVK/NOPB National Semiconductor, DS50PCI402EVK/NOPB Datasheet
DS50PCI402EVK/NOPB
Specifications of DS50PCI402EVK/NOPB
Related parts for DS50PCI402EVK/NOPB
DS50PCI402EVK/NOPB Summary of contents
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... Gen1 data rates to Gen2 without reducing their physical reach. This is true for FR4 applications such as back- planes, as well as cable interconnect. Typical Application © 2010 National Semiconductor Corporation DS50PCI402 Features ■ Input and Output signal conditioning increases PCIe reach in backplanes and cables ■ ...
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Block Diagram - Detail View Of Channel ( www.national.com 2 30107386 ...
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Pin Diagram Ordering Information NSID Qty DS50PCI402SQ Tape & Reel Supplied As 2,000 Units DS50PCI402SQE Tape & Reel Supplied As 250 Units DS50PCI402 Pin Diagram 54 lead Spec NOPB NOPB 3 30107392 Package SQA54A SQA54A www.national.com ...
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Pin Descriptions Pin Name Pin Number Differential High Speed I/O's IA_0+, IA_0- , 10, 11 IA_1+, IA_1-, 12, 13 IA_2+, IA_2-, 15, 16 IA_3+, IA_3- 17, 18 OA_0+, OA_0-, 35, 34 OA_1+, OA_1-, 33, 32 OA_2+, OA_2-, 31, 30 OA_3+, ...
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Pin Name Pin Number DEMA0, DEMA1 49, 50 DEMB0, DEMB1 53, 54 RATE 21 Control Pins — Both Modes (LVCMOS) RXDETA,RXDETB 22,23 PRSNT 52 ENRXDET 26 TXIDLEA,TXIDLEB 24,25 Analog SD_TH 27 Power VDD 9, 14,36, 41, 51 GND DAP Notes: ...
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Functional Description The DS50PCI402 is a low power media compensation 4 lane repeater optimized for PCI Express Gen 1 and Gen 2 media including lossy FR-4 printed circuit board backplanes and balanced cables. The DS50PCI402 operates in two modes: Pin ...
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TABLE 3. Equalization Settings with GST=3 for Pins or SMBus Registers EQ Setting EQ Gain (dB) EQ1 EQ0 GST BST 1.25 GHz [1:0] [2:0] 11 000 6 001 8.5 11 010 10 011 12.4 ...
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TXIDLEA/B 0 This state is for lossy media, dedicated Idle threshold detect circuit disabled, output follows input based Float Float enables automatic idle detection. Idle on the input is passed to the output. This is the recommended default state. Output ...
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Receiver Detection The Rx detection process is a feature that can set the number of active channels on the DS50PCI402. By sensing the pres- ence of a valid PCIe load on the output, the channel can be automatically enabled for ...
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Manual Control Of RXDETA PCIe Environment In some cases manual control of RXDETA/B may be desir- able. In order for upstream and downstream PCIe subsys- tems to communicate in a cabling environment, the PCIe specification includes several auxiliary ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) LVCMOS Input/Output Voltage CML Input Voltage CML Input Current LPDS Output Voltage Analog (SD_TH) Junction Temperature Storage Temperature Lead Temperature Range Soldering (4 sec ...
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Symbol Parameter CML RECEIVER INPUTS (IN_n+, IN_n package plus Si RX-DIFF differential return loss RL Common mode Rx RX-CM return loss common mode RX-DC impedance differential RX-DIFF-DC impedance V Differential Rx peak ...
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Symbol Parameter V Absolute Delta of DC TX-CM-DC- LINE-DELTA Common Mode Voltage between Tx+ and Tx- T Max time to transition to TX-IDLE-SET-TO -IDLE valid diff signaling after leaving Electrical Idle T Max time to transition to TX-IDLE-TO -DIFF-DATA valid ...
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Symbol Parameter DE-EMPHASIS Residual Deterministic Jitter at 5 Gbps DJD1 Residual Deterministic Jitter at 2.5 Gbps DJD2 Residual Deterministic Jitter at 5 Gbps DJD3 Residual Deterministic Jitter at 2.5 Gbps DJD4 Note 1: “Absolute Maximum Ratings” indicate limits beyond which ...
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Electrical Characteristics — Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter SERIAL BUS INTERFACE DC SPECIFICATIONS V Data, Clock Input Low Voltage IL V Data, Clock Input High Voltage IH I Current ...
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Timing Diagrams www.national.com FIGURE 3. CML Output Transition Times FIGURE 4. Propagation Delay Timing Diagram FIGURE 5. Idle Timing Diagram 16 30107302 30107303 30107304 ...
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FIGURE 6. Input and Output Return Loss Setup FIGURE 7. SMBus Timing Parameters 17 30107354 30107394 www.national.com ...
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System Management Bus (SMBus) and Configuration Registers The System Management Bus interface is compatible to SM- Bus 2.0 physical layer specification. ENSMB must be pulled high to enable SMBus mode and allow access to the config- uration registers. The DS50PCI402 ...
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IDLE AND RATE DETECTION TO EXTERNAL PINS The functions of IDLE and RATE detection to external pins for monitoring can be supported in SMBus mode. The external GPIO pins of 19, 20, 46 and 47 will be changed and they ...
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Address Register Name Bit (s) Field 0x00 Reset 7:1 0 0x01 PWDN Channels 7:0 0x02 PWDN Control 7:1 0 0x08 Pin Control Override 7 1:0 www.national.com TABLE 9. SMBus Register Map Type Defaul Description t Reserved R/W ...
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CH0 - CHB0 7:6 IDLE RATE Select 0x0F CH0 - CHB0 7:6 EQ Control 5:0 0x10 CH0 - CHB0 7 VOD Control 5:0 0x11 CH0 - CHB0 7:0 DE Control 0x12 CH0 - CHB0 ...
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CH1 - CHB1 7:6 IDLE RATE Select 0x16 CH1 - CHB1 7:6 EQ Control 5:0 0x17 CH1 - CHB1 7 VOD Control 5:0 0x18 CH1 - CHB1 7:0 DE Control 0x19 CH1 - CHB1 ...
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CH2 - CHB2 7:6 IDLE RATE Select 0x1D CH2 - CHB2 7:6 EQ Control 5:0 0x1E CH2 - CHB2 7 VOD Control 5:0 0x1F CH2 - CHB2 7:0 DE Control 0x20 CH2 - CHB2 ...
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CH3 - CHB3 7:6 IDLE RATE Select 0x24 CH3 - CHB3 7:6 EQ Control 5:0 0x25 CH3 - CHB3 7 VOD Control 5:0 0x26 CH3 - CHB3 7:0 DE Control 0x27 CH3 - CHB3 ...
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CH4 - CHA0 7:6 IDLE RATE Select 0x2C CH4 - CHA0 7:6 EQ Control 5:0 0x2D CH4 - CHA0 7 VOD Control 5:0 0x2E CH4 - CHA0 7:0 DE Control 0x2F CH4 - CHA0 ...
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CH5 - CHA1 7:6 IDLE RATE Select 0x33 CH5 - CHA1 7:6 EQ Control 5:0 0x34 CH5 - CHA1 7 VOD Control 5:0 0x35 CH5 - CHA1 7:0 DE Control 0x36 CH5 - CHA1 ...
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CH6 - CHA2 7:6 IDLE RATE Select 0x3A CH6 - CHA2 7:6 EQ Control 5:0 0x3B CH6 - CHA2 7 VOD Control 5:0 0x3C CH6 - CHA2 7:0 DE Control 0x3D CH6 - CHA2 ...
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CH7 - CHA3 7:6 IDLE RATE Select 0x41 CH7 - CHA3 7:6 EQ Control 5:0 0x42 CH7 - CHA3 7 VOD Control 5:0 0x43 CH7 - CHA3 7:0 DE Control 0x44 CH7 - CHA3 ...
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Global VOD Adjust 7:2 1:0 R/W 0x02 Reserved Set bits to 0. VOD Adjust 00 = -25. -12. +0.0% (Default +12.5% 29 www.national.com ...
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Applications Information GENERAL RECOMMENDATIONS The DS50PCI402 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer to the information ...
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Typical Performance Eye Diagrams and Curves DS50PCI402 Return Loss FIGURE 9. Receiver Return Loss Mask for 5.0 Gbps FIGURE 10. Transmitter Return Loss Mask for 5.0 Gbps 30107350 31 30107351 www.national.com ...
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Physical Dimensions Order Number DS50PCI402SQ (Tape and Reel 2000 units) Order Number DS50PCI402SQE (Tape and Reel 250 units) (See AN-1187 for PCB Design and Assembly Recommendations) www.national.com inches (millimeters) unless otherwise noted NS Package Number SQA54A 32 ...
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Notes 33 www.national.com ...
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