EVAL-AD5232-10EBZ Analog Devices Inc, EVAL-AD5232-10EBZ Datasheet - Page 8

• Manufacturer Part Number: EVAL-AD5232-10EBZ
• Description: BOARD EVALUATION FOR AD5232-10
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5232-10EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: AD5232
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

AD5232
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
CLK
SDI
SDO
GND
V
A1
W1
B1
B2
W2
A2
V
WP
PR
CS
RDY
SS
DD
Description
Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
Serial Data Input. The MSB is loaded first.
Serial Data Output. This open-drain output requires an external pull-up resistor. Command Instruction 9 and Command
Instruction 10 activate the SDO output (see Table 8). Other commands shift out the previously loaded SDI bit pattern
delayed by 16 clock pulses, allowing daisy-chain operation of multiple packages.
Ground, Logic Ground Reference.
Negative Power Supply. Connect to 0 V for single-supply applications.
Terminal A of RDAC1.
Wiper Terminal W of RDAC1, ADDR (RDAC1) = 0x0.
Terminal B of RDAC1.
Terminal B of RDAC2.
Wiper Terminal W of RDAC2, ADDR (RDAC2) = 0x1.
Terminal A of RDAC2.
Positive Power Supply.
Write Protect. When active low, WP prevents any changes to the present register contents, except PR, Command
Instruction 1, and Command Instruction 8, which refresh the RDACx register from EEMEM. Execute an NOP instruction
(Command Instruction 0) before returning WP to logic high.
Hardware Override Preset. Refreshes the scratch pad register with current contents of the EEMEMx register. Factory
default loads Midscale 0x80 until EEMEMx is loaded with a new value by the user (PR is activated at the logic high
transition).
Serial Register Chip Select, Active Low. Serial register operation takes place when CS returns to logic high.
Ready. This active-high, open-drain output requires a pull-up resistor. Identifies completion of Command Instruction 2,
Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and PR.
GND
SDO
CLK
V
SDI
W1
A1
B1
SS
Figure 4. Pin Configuration
1
4
5
2
3
6
7
8
Rev. A | Page 8 of 24
(Not to Scale)
AD5232
TOP VIEW
16
14
15
13
12
11
10
9
RDY
CS
PR
WP
V
A2
W2
B2
DD