EVAL-AD5232-10EBZ

Manufacturer Part NumberEVAL-AD5232-10EBZ
DescriptionBOARD EVALUATION FOR AD5232-10
ManufacturerAnalog Devices Inc
EVAL-AD5232-10EBZ datasheet
 


Specifications of EVAL-AD5232-10EBZ

Main PurposeDigital PotentiometerUtilized Ic / PartAD5232
Lead Free Status / RoHS StatusLead free / RoHS CompliantSecondary Attributes-
Embedded-Primary Attributes-
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AD5232
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin
No.
Mnemonic
Description
1
CLK
Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2
SDI
Serial Data Input. The MSB is loaded first.
3
SDO
Serial Data Output. This open-drain output requires an external pull-up resistor. Command Instruction 9 and Command
Instruction 10 activate the SDO output (see Table 8). Other commands shift out the previously loaded SDI bit pattern
delayed by 16 clock pulses, allowing daisy-chain operation of multiple packages.
4
GND
Ground, Logic Ground Reference.
5
V
Negative Power Supply. Connect to 0 V for single-supply applications.
SS
6
A1
Terminal A of RDAC1.
7
W1
Wiper Terminal W of RDAC1, ADDR (RDAC1) = 0x0.
8
B1
Terminal B of RDAC1.
9
B2
Terminal B of RDAC2.
10
W2
Wiper Terminal W of RDAC2, ADDR (RDAC2) = 0x1.
11
A2
Terminal A of RDAC2.
12
V
Positive Power Supply.
DD
13
WP
Write Protect. When active low, WP prevents any changes to the present register contents, except PR, Command
Instruction 1, and Command Instruction 8, which refresh the RDACx register from EEMEM. Execute an NOP instruction
(Command Instruction 0) before returning WP to logic high.
14
PR
Hardware Override Preset. Refreshes the scratch pad register with current contents of the EEMEMx register. Factory
default loads Midscale 0x80 until EEMEMx is loaded with a new value by the user (PR is activated at the logic high
transition).
15
CS
Serial Register Chip Select, Active Low. Serial register operation takes place when CS returns to logic high.
16
RDY
Ready. This active-high, open-drain output requires a pull-up resistor. Identifies completion of Command Instruction 2,
Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and PR.
CLK
1
16
RDY
SDI
2
CS
15
SDO
PR
3
14
AD5232
TOP VIEW
GND
4
13
WP
(Not to Scale)
V
5
12
V
SS
DD
A1
6
11
A2
W1
7
10
W2
B1
8
9
B2
Figure 4. Pin Configuration
Rev. A | Page 8 of 24