CDB5467U Cirrus Logic Inc, CDB5467U Datasheet - Page 10

• Manufacturer Part Number: CDB5467U
• Description: BOARD EVAL FOR CS5467 ADC
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5467U

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5467
• Primary Attributes: Watt-Hour Meter
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Product: Data Conversion Development Tools
• Maximum Clock Frequency: 4 MHz
• Interface Type: USB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• For Use With/related Products: CS5467
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1555; CDB-5467U

DIGITAL CHARACTERISTICS
Notes: 10. All measurements performed under static conditions.
10
Master Clock Characteristics
Master Clock Frequency
Master Clock Duty Cycle
CPUCLK Duty Cycle
Filter Characteristics
Phase Compensation Range
Input Sampling Rate
Digital Filter Output Word Rate
High-pass Filter Corner Frequency
Full-scale DC Calibration Range (Referred to Input)
Channel-to-channel Time-shift Error
Input/Output Characteristics
High-level Input Voltage
Low-level Input Voltage (VD = 5 V)
Low-level Input Voltage (VD = 3.3 V)
High-level Output Voltage
Low-level Output Voltage
Input Leakage Current
3-state Leakage Current
Digital Output Pin Capacitance
• Min / Max characteristics and specifications are guaranteed over all
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• DCLK = 4.096 MHz.
11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is
12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification.
13. The frequency of CPUCLK is equal to MCLK.
14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is
15. Configuration register (Config) bits PC[6:0] are set to “0000000”.
16. The MODE pin is pulled low by an internal resistor.
used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between
2.5 MHz - 5.0 MHz.
limited by the full-scale signal applied to the input.
Parameter
All Pins Except XIN and SCLK and RESET
All Pins Except XIN and SCLK and RESET
All Pins Except XIN and SCLK and RESET
Internal Gate Oscillator (Note 11)
I
out
(60 Hz, OWR = 4000 Hz)
I
= -2.5 mA (VD = +3.3V)
out
= -5 mA (VD = +5V)
SCLK and RESET
SCLK and RESET
SCLK and RESET
DCLK = MCLK/K
(Note 12 and 13)
(Both channels)
I
out
(Note 15)
(Note 14)
(Note 16)
= +5 mA
-3 dB
XIN
XIN
XIN
Symbol
DCLK
FSCR
OWR
V
C
V
V
V
V
I
I
OZ
OH
OL
out
in
Recommended Operating
IH
IL
IL
(VD+) – 0.5
(VD+) - 1.0
0.6 VD+
0.8 VD+
Min
-5.4
2.5
40
40
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DCLK/1024
DCLK/8
4.096
Typ
0.5
1.0
Conditions.
±1
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.2 VD+
0.2 VD+
+5.4
Max
0.48
100
±10
±10
0.8
1.5
0.3
0.4
0.4
CS5467
20
60
60
-
-
-
-
-
-
-
-
DS714F1
%FS
MHz
Unit
Hz
Hz
Hz
µA
µA
pF
µs
%
%
V
V
V
V
V
V
V
V
V
V
V
V
°