BOARD EVAL FOR AD9951

AD9551/PCBZ

Manufacturer Part NumberAD9551/PCBZ
DescriptionBOARD EVAL FOR AD9951
ManufacturerAnalog Devices Inc
AD9551/PCBZ datasheet
 

Specifications of AD9551/PCBZ

Main PurposeTiming, Clock GeneratorEmbeddedNo
Utilized Ic / PartAD9551Primary Attributes2 Inputs, 2 Outputs, VCO
Secondary AttributesGraphical User Interface, USB InterfaceSilicon ManufacturerAnalog Devices
Application Sub TypeClock GeneratorKit Application TypeClock & Timing
Silicon Core NumberAD9551Kit ContentsBoard
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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FEATURES
Translation between any two standard network rates
Dual reference inputs and dual clock outputs
Pin programmable for standard network rate translation
SPI programmable for arbitrary rational rate translation
Output frequencies from 10 MHz to 900 MHz
Input frequencies from 19.44 MHz to 806 MHz
On-chip VCO
Meets OC-192 high band jitter generation requirement
Supports standard forward error correction (FEC) rates
Supports holdover operation
Supports hitless switchover and phase build-out (even with
unequal reference frequencies)
SPI-compatible 3-wire programming interface
Single supply (3.3 V)
APPLICATIONS
Multiservice switches
Multiservice routers
Exact network clock frequency translation
General-purpose frequency translation
GENERAL DESCRIPTION
The AD9551 accepts one or two reference input signals to synthe-
size one or two output signals. The AD9551 uses a fractional-N
PLL that precisely translates the reference frequency to the desired
output frequency. The input receivers and output drivers provide
both single-ended and differential operation.
REFA
REFB
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks ar
e the property of their respective owners.
Multiservice Clock Generator
Reference conditioning and switchover circuitry internally
synchronizes the two references so that if one reference fails,
there is virtually no phase perturbation at the output.
The AD9551 uses an external crystal and an internal DCXO to
provide for holdover operation. If both references fail, the device
maintains a steady output signal.
The AD9551 provides pin-selectable, preset divider values for
standard (and FEC adjusted) network frequencies. The pin-
selectable frequencies include any combination of 15 possible
input frequencies and 16 possible output frequencies. A SPI
interface provides further flexibility by making it possible to
program almost any rational input/output frequency ratio.
The AD9551 is a clock generator that employs fractional-N-based
phase-locked loops (PLL) using sigma-delta (Σ-Δ) modulators
(SDMs). The fractional frequency synthesis capability enables
the device to meet the frequency and feature requirements for
multiservice switch applications. The AD9551 precisely generates
a wide range of standard frequencies when using any one of those
same standard frequencies as a timing base (reference). The
primary challenge of this function is the precise generation of the
desired output frequency because even a slight output frequency
error can cause problems for downstream clocking circuits in
the form of bit or cycle slips. The requirement for exact frequency
translation in such applications necessitates the use of a frac-
tional-N-based PLL architecture with variable modulus.
BASIC BLOCK DIAGRAM
CRYSTAL
(26MHz)
REFERENCE
CONDITIONING
HOLDOVER
PLL
AND SWITCH-
LOOP
OVER
PIN-DEFINED AND SERIAL
PROGRAMMING
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9551
OUT1
OUTPUT
CIRCUITRY
OUT2
AD9551
www.analog.com
©2009 Analog De
vices, Inc. All rights reserved.

AD9551/PCBZ Summary of contents

  • Page 1

    FEATURES Translation between any two standard network rates Dual reference inputs and dual clock outputs Pin programmable for standard network rate translation SPI programmable for arbitrary rational rate translation Output frequencies from 10 MHz to 900 MHz Input frequencies from ...

  • Page 2

    AD9551 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Basic Block Diagram ........................................................................ 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 Reference Clock Input Characteristics ...................................... 4 Output Characteristics ................................................................. ...

  • Page 3

    The AD9551 is easily configured using the external control pins (A[3:0], B[3:0], and Y[3:0]). The logic state of these pins sets pre- defined divider values that establish a specific input-to-output frequency ratio. For applications requiring other frequency ratios, the user ...

  • Page 4

    AD9551 SPECIFICATIONS Minimum and maximum values apply for full range of supply voltage and operating temperature variation. Typical values apply for VDD = 3 25°C, unless otherwise noted. A REFERENCE CLOCK INPUT CHARACTERISTICS Table 1. Parameter FREQUENCY ...

  • Page 5

    Parameter Duty Cycle 1 Rise/Fall Time (20% to 80%) 1 The listed values are for the slower edge (rise or fall). JITTER CHARACTERISTICS (180 HZ LOOP BANDWIDTH) Table 3. Parameter JITTER GENERATION 12 kHz to 20 MHz 50 kHz to ...

  • Page 6

    AD9551 LOGIC INPUT PINS Table 6. Parameter 1 INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current The A[3:0], B[3:0], Y[3:0], and OUTSEL pins have 100 ...

  • Page 7

    Parameter Input Logic 1 Current Input Logic 0 Current Input Capacitance Output Output Logic 1 Voltage Output Logic 0 Voltage SERIAL CONTROL PORT TIMING Table 10. Parameter SCLK Clock Rate, 1/t CLK Pulse Width High, t HIGH Pulse Width Low, ...

  • Page 8

    AD9551 ABSOLUTE MAXIMUM RATINGS Table 11. Parameter Supply Voltage (VDD) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Stresses above those listed under Absolute Maximum Ratings Rating may cause permanent damage to ...

  • Page 9

    PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 12. Pin Function Descriptions Pin 1 No. Mnemonic Type VDD P 9, 23, 27, 34 30, 31 GND P 4 REFA I 3 REFA I 5 REFB I 6 REFB ...

  • Page 10

    AD9551 Pin 1 No. Mnemonic Type Exposed Die Pad power ...

  • Page 11

    TYPICAL PERFORMANCE CHARACTERISTICS CARRIER 622.080005MHz 0.8813dBm –20 RMS JITTER: –30 0.827ps (12kHz TO 20MHz) –40 0.618ps (50kHz TO 80MHz) –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 100 1k 10k 100k FREQUENCY OFFSET FROM ...

  • Page 12

    AD9551 35 30 LVPECL 25 20 LVDS (STRONG LVDS (WEAK) 5 100 FREQUENCY (MHz) Figure 10. Supply Current vs. Output Frequency— LVPECL and LVDS (10 pF Load) 1.6 LVPECL 1.4 1.2 LVDS (STRONG) 1.0 0.8 LVDS (WEAK) 0.6 ...

  • Page 13

    Figure 16. Typical Output Waveform—LVPECL (805 MHz) 1.25ns/DIV Figure 17. Typical Output Waveform—CMOS (250 MHz Load) Figure 18. Typical Output Waveform—LVDS (805 MHz, 3.5 mA Drive Current) Rev Page AD9551 500ps/DIV ...

  • Page 14

    AD9551 PRESET FREQUENCY RATIOS The frequency selection pins (A[3:0], B[3:0], and Y[3:0]) allow the user to hardwire the device for preset input and output divider values based on the pin logic states. The A[3:0] pins control the REFA dividers, the ...

  • Page 15

    The Y[3:0] pins select the divider values for the feedback path of the output PLL, as well as for the OUT1 dividers, P OUT2 divider defaults to unity unless otherwise program- 2 med using the serial port. Table ...

  • Page 16

    AD9551 THEORY OF OPERATION OPERATING MODES The AD9551 provides the following fundamental operating modes: • Normal mode • 19.44 MHz mode Mode selection depends on the state of the frequency selection pins (A[3:0] and B[3:0]). If all four of the ...

  • Page 17

    REFA, REFA REFERENCE MONITOR ÷ REFB, REFB Synchronization/Switchover Control Figure 19, which is a block diagram of the hitless reference switch- over circuit, shows that reference synchronization occurs after the input reference dividers. The synchronization and switchover functionality relies ...

  • Page 18

    AD9551 The reference DLL measures the period of the active reference and produces the required N/2 delay value. When the reference DLL locks, the following three events occur: • Both DLL A and DLL B are enabled. • The DLL ...

  • Page 19

    Input PLL The input PLL consists of a phase/frequency detector (PFD), a digital loop filter, and a digitally controlled crystal oscillator (DCXO) that operates in a closed loop. The loop contains a 2× frequency multiplier, a 2× frequency divider, a ...

  • Page 20

    AD9551 The gain of the output PLL is proportional to the current delivered by the charge pump. The user can override the default charge pump current setting, and, thereby, the PLL gain, by using Register 0x0A[7:0]. The output PLL has ...

  • Page 21

    HOLDOVER MODE In the absence of both input references, the device enters holdover mode. Holdover is a secondary function that is provided by the input PLL. Because the DCXO has an external crystal as its fre- quency source, it continues ...

  • Page 22

    AD9551 The value of K depends on the device configuration, as shown in Table 16. Table 16. Configuring the Value of K Mode f K CRYSTAL 19.44 MHz 52 MHz 1300/243 325/243 50 MHz 1250/243 625/486 49.86 MHz 277/54 277/216 ...

  • Page 23

    Determine the feedback divider values for the output PLL. Repeat this step for each ODF when multiple ODFs exist (for example, 35, 36, and 40, in the case of Table 17). To calculate the feedback divider values for a ...

  • Page 24

    AD9551 As in Step 4, use long division to convert the fraction, X integer, N, and a proper fraction, R/Y (R and Y a integers). The same caution giv en in Step 4 applies here, regarding the need ...

  • Page 25

    APPLICATIONS INFORMATION THERMAL PERFORMANCE Table 18. Thermal Parameters for the 40-Lead LFCSP Package Symbol Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board θ Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) JA θ Junction-to-ambient thermal ...

  • Page 26

    AD9551 SERIAL CONTROL PORT The AD9551 serial control port is a flexible, synchronous, serial communications port that allows an easy interface to many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB first or ...

  • Page 27

    By default, a read request reads the register value that is currently in use by the AD9551. However, setting Register 0x04[ causes the buffered registers to be read instead. The buffered registers are the ones that take effect ...

  • Page 28

    AD9551 CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 26. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data CS SCLK DON'T CARE SDIO R ...

  • Page 29

    REGISTER MAP A bit that is labeled “aclr” active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns Logic 0 state upon completion of the indicated task. Table 22. ...

  • Page 30

    AD9551 Addr. Register (MSB) (Hex) Name Bit 7 Bit 6 0x19 Output PLL Enable SPI Enable SPI control control control of OUT1 of OUT2 dividers divider 0x1A Input Receiver receiver and reset band gap (aclr) 0x1B DCXO Disable Enable SPI ...

  • Page 31

    Addr. Register (MSB) (Hex) Name Bit 7 Bit 6 0x2E REFA delay Enable SPI control of REFA delay 0x2F REFA delay REFA delay control[1:0] 0x30 REFB delay Enable SPI control of REFB delay 0x31 REFB delay REFB delay control[1:0] 0x32 ...

  • Page 32

    AD9551 REGISTER MAP DESCRIPTIONS Control bit functions are active high, and register address values are always hexadecimal, unless otherwise noted. Serial Port Control (Register 0x00 to Register 0x05) Table 23. Address Bit Bit Name 0x00 7 Unused 6 LSB first ...

  • Page 33

    Address Bit Bit Name 0x0C 7 Unused 6 CP offset current polarity [5:4] CP offset current 3 Enable CP offset current control 2 Reserved 1 Reserved 0 Reserved 0x0D [7:6] Antibacklash control [5:1] Unused 0 Output PLL lock detector power-down ...

  • Page 34

    AD9551 Output PLL Control (Register 0x11 to Register 0x19) Table 26. Address Bit Bit Name 0x11 [7:0] N 0x12 [7:0] MOD 0x13 [7:0] MOD 0x14 [7:4] MOD 3 Enable SPI control of output frequency 2 Bypass output SDM 1 Disable ...

  • Page 35

    Input Receiver and Band Gap (Register 0x1A) Table 27. Address Bit Bit Name 0x1A 7 Receiver reset [6:2] Band gap voltage adjust 1 Enable receiver power-down 0 Enable SPI control of band gap voltage DCXO Control (Register 0x1B to Register ...

  • Page 36

    AD9551 REFA Frequency Control (Register 0x1E to Register 0x25) Table 29. Address Bit Bit Name 0x1E 7 Enable SPI control of REFA SDM 6 Bypass REFA SDM 5 Enable REFA SDM 4 Enable REFB 3 Unused 2 Disable REF SDM ...

  • Page 37

    REFB Frequency Control (Register 0x26 to Register 0x2D) Table 30. Address Bit Bit Name 0x26 7 Enable SPI control of REFB SDM 6 Bypass REFB SDM 5 Enable REFB SDM 4 Enable REFA [3:0] Unused 0x27 [7:0] FRACB 0x28 [7:0] ...

  • Page 38

    AD9551 OUT1 Driver Control (Register 0x32) Table 33. Address Bit Bit Name 0x32 7 OUT1 drive strength 6 OUT1 power-down [5:3] OUT1 mode control [2:1] OUT1 CMOS polarity 0 Enable SPI control of OUT1 driver control Input PLL Control (Register ...

  • Page 39

    OUT2 Driver Control (Register 0x34) Table 35. Address Bit Bit Name 0x34 7 OUT2 drive strength 6 OUT2 power-down [5:3] OUT2 mode control [2:1] OUT2 CMOS polarity 0 Enable SPI control of OUT2 driver control Description Controls the output drive ...

  • Page 40

    ... ORDERING GUIDE Model Temperature Range 1 AD9551BCPZ –40°C to +85°C 1 AD9551BCPZ-REEL7 –40°C to +85°C 1 AD9551/PCBZ RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 6.00 BSC SQ 0.60 MAX 0.50 BSC 5 ...