AD9551/PCBZ Analog Devices Inc, AD9551/PCBZ Datasheet - Page 33

BOARD EVAL FOR AD9951

AD9551/PCBZ

Manufacturer Part Number
AD9551/PCBZ
Description
BOARD EVAL FOR AD9951
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9551/PCBZ

Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9551
Primary Attributes
2 Inputs, 2 Outputs, VCO
Secondary Attributes
Graphical User Interface, USB Interface
Silicon Manufacturer
Analog Devices
Application Sub Type
Clock Generator
Kit Application Type
Clock & Timing
Silicon Core Number
AD9551
Kit Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Address
0x0C
0x0D
VCO Control (Register 0x0E to Register 0x10)
Table 25.
Address
0x0E
0x0F
0x10
Bit
7
6
[5:4]
3
2
1
0
[7:6]
[5:1]
0
Bit
7
6
[5:3]
2
1
0
[7:2]
[1:0]
[7:1]
0
Bit Name
Unused
CP offset current polarity
CP offset current
Enable CP offset current control
Reserved
Reserved
Reserved
Antibacklash control
Unused
Output PLL lock detector
power-down
Bit Name
Calibrate VCO
Enable automatic level control
Automatic level control
threshold
Enable SPI control of VCO
calibration
Boost VCO supply
Enable SPI control of VCO band
setting
VCO level control
Unused
VCO band control
Unused
Description
Unused.
Selects the polarity of the charge pump offset current of the output PLL.
0 = pump up (default).
1 = pump down.
This bit is ineffective unless Bit 3 = 1.
Controls the magnitude of the charge pump offset current of the output PLL as a
fraction of the value in Register 0x0A. Ineffective unless Bit 3 = 1.
00 = 1/2 (default).
01 = 1/4.
10 = 1/8.
11 = 1/16.
Controls functionality of Bits[6:4].
0 = the device automatically controls charge pump offset current (default).
1 = charge pump offset current defined by Bits[6:4].
Enables PFD up divide-by-2 (reserved for test).
Enables PFD down divide-by-2 (reserved for test).
Enables feedback divide-by-2 (reserved for test).
Controls the PFD antibacklash period of the output PLL.
00 = minimum (default).
01 = low.
10 = high.
11 = maximum.
These bits are ineffective unless Register 0x0B[6] = 1.
Unused.
Controls power-down of the output PLL’s lock detector.
0 = lock detector active (default).
1 = lock detector powered down.
Description
Initiates VCO calibration (this is an autoclearing bit). This bit is ineffective unless Bit 2 = 1.
Enables automatic level control of the VCO.
0 = VCO level defined by Register 0x0F[7:2].
1 = the device automatically controls the VCO level (default).
Controls the VCO threshold detector level. The default is 110. Note that the function-
ality of Bit 4 is inverted; that is, the minimum is 010, and the maximum is 101.
Enables functionality of Bit 7.
0 = the device automatically performs VCO calibration (default).
1 = Bit 7 controls VCO calibration.
Selects VCO supply voltage.
0 = normal supply voltage (default).
1 = increase supply voltage by 100 mV.
Controls VCO band setting functionality.
0 = the device automatically selects the VCO band (default).
1 = VCO band defined by Register 0x10[7:1].
Unused.
Controls the VCO amplitude from minimum (00 0000) to maximum (11 1111). The
default is 10 0000. These bits are ineffective unless Register 0x0E[6] = 0.
Unused.
Controls the VCO frequency band from minimum (000 0000) to maximum (111 1111).
The default is 100 0000.
Rev. B | Page 33 of 40
AD9551

Related parts for AD9551/PCBZ