AD9959/PCBZ Analog Devices Inc, AD9959/PCBZ Datasheet - Page 11

• Manufacturer Part Number: AD9959/PCBZ
• Description: BOARD EVALUATION FOR AD9959
• Manufacturer: Analog Devices Inc

Specifications of AD9959/PCBZ

• Design Resources: Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9959
• Primary Attributes: 10-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 4 Channels
• Silicon Core Number: AD9959
• Application Sub Type: Frequency Synthesizer
• Kit Contents: Board, AD9959 / PCB Installation Software
• Silicon Manufacturer: Analog Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD9959/PCB; AD9959/PCB; Q2548077

Channel Control
The Channel Control window provides control of the features
that affect the AD9959 at a channel-specific level. The following
describes the sections of the Channel Control window as they
are numerically indexed in Figure 21.
1. Channel Select
Use the Channel Select tabs to select which specific channel
options to configure. The AD9959 has four independent
channels: Channel <0:3>. The default channel select tab
setting is Channel 0.
2. Pwr Down
Use the Pwr Down section to power down the digital logic
(check Digital box) or the DAC circuitry (check DAC box).
Upon default, both of these boxes are unchecked, indicating
that the digital logic and the DAC circuitry of that channel are
enabled (powered up).
3. Modulation Output Type
The Modulation Output Type box controls what type of
modulation is performed on the channel’s output. Select Phase,
Frequency, Amplitude, or None (Single Tone) depending
upon which type of modulation you want. The level of
modulation for the channel is set using the Chip Level Control
window under the Modulation Configuration section in the
Level box.
4. Linear Sweep Options
Use the Linear Sweep Options section to control the linear
sweep features. Select Enable Linear Sweep to turn on the
linear sweep function and the additional associated options (see
Figure 22).
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3
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Figure 21. Channel Control Window
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Select Linear Sweep No Dwell to enable this feature, see the
Linear Sweep No Dwell Mode section of the AD9959 data sheet
for more information regarding the no dwell feature.
When you select Load SRR @ I/O Update,
sweep ramp rate register are loaded into the sweep ramp rate
timer every time an I/O_UPDATE is sent to the device.
The Clear Sweep Accumulator and Auto Clear Sweep
Accumulator have the same basic functionality as described in
the All Channel Accumulator Control section of the Chip Level
Control window. The difference is that here the function is
channel-specific.
See the Linear Sweep (Shaped) Modulation Mode section of the
AD9959 data sheet for a detailed explanation of this mode.
5. Pipe-Line Latency Control
When you check the Match Pipe Delays box in the Pipe
Latency Control section, the pipeline delay for updates to
frequency, amplitude, and phase will be equal, but only for the
channels operating in single tone mode. The default setting of
this box is unchecked, meaning the pipeline delay for updates to
frequency, amplitude, and phase will not be equal.
Figure 22.
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the contents of the
AD9959/PCB