AD9911/PCBZ Analog Devices Inc, AD9911/PCBZ Datasheet
AD9911/PCBZ
Specifications of AD9911/PCBZ
Related parts for AD9911/PCBZ
AD9911/PCBZ Summary of contents
Page 1
FEATURES Patented SpurKiller technology Multitone generation Test-tone modulation Up to 800 Mbps data throughput Matched latencies for frequency/phase/amplitude changes Linear frequency/phase/amplitude sweeping capability levels of FSK, PSK, ASK Programmable DAC full-scale current 32-bit frequency tuning resolution 14-bit ...
Page 2
AD9911 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Equivalent Input and Output Circuits....................................... 9 Pin Configuration and ...
Page 3
GENERAL DESCRIPTION The DDS acts as a high resolution frequency divider with the REF_CLK as the input and the DAC providing the output. The REF_CLK input can be driven directly or used in combination with an integrated REF_CLK multiplier (PLL). ...
Page 4
AD9911 SPECIFICATIONS AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; R multiplier bypassed), unless otherwise noted. Table 1. Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REF_CLK Multiplier Bypassed REF_CLK Multiplier Enabled Internal VCO Output ...
Page 5
Parameter NARROWBAND SFDR 1.1 MHz Analog Output (±10 kHz) 1.1 MHz Analog Output (±50 kHz) 1.1 MHz Analog Output (±250 kHz) 1.1 MHz Analog Output (±1 MHz) 15.1 MHz Analog Output (±10 kHz) 15.1 MHz Analog Output (±50 kHz) 15.1 ...
Page 6
AD9911 Parameter Residual Phase Noise @ 15.1 MHz (f OUT REF_CLK Multiplier Enabled 5× 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset Residual Phase Noise @ 40.1 MHz (f OUT with REF_CLK Multiplier Enabled 5× 1 ...
Page 7
Parameter I/O PORT TIMING CHARACTERISTICS Maximum Frequency Clock (SCLK) Minimum SCLK Pulse Width Low (t ) PWL Minimum SCLK Pulse Width High (t PWH Minimum Data Set-Up Time ( Minimum Data Hold Time Minimum CSB Set-Up Time (t ...
Page 8
AD9911 Parameter DATA LATENCY (PIPELINE DELAY) SINGLE- TONE MODE 2, 3 Frequency, Phase, and Amplitude Words to DAC Output with Matched Latency Enabled Frequency Word to DAC Output with Matched Latency Disabled Phase Offset Word to DAC Output with Matched ...
Page 9
ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 49) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Output Current Storage Temperature Operating Temperature Lead Temperature (10 sec Soldering) θ JA θ JC ESD CAUTION ESD ...
Page 10
AD9911 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions Pin No. Mnemonic 1 SYNC_IN 2 SYNC_OUT 3 MASTER_RESET 4 PWR_DWN_CTL 11, 13, 14, AVDD 15, 19, 21, 26, 29, 30, 31, 33, 37, 39 ...
Page 11
Pin No. Mnemonic 6, 10, 12, 16, 28 40, 41, 42, 43 P0, P1, P2 I/O_UPDATE SCLK 49 DVDD_I/O 50 SDIO_0 51, 52, 53 SDIO_1, SDIO_2, SDIO_3 54 SYNC_CLK I/O Description N/A No ...
Page 12
AD9911 TYPICAL PERFORMANCE CHARACTERISTICS DELTA 1 (T1) RBW REF LVL –71.73dB VBW 0dBm 4.50901804MHz SWT 0 1 –10 –20 –30 –40 –50 –60 –70 1 –80 –90 –100 START 0Hz 25MHz/DIV Figure 1.1 MHz 500 ...
Page 13
REF LVL DELTA 1 (T1) RBW 500Hz 0dBm –84.73dB VBW 500Hz 254.50901604kHz SWT 20s 0 1 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 1.1MHz 100kHz/DIV Figure 13 1.1 MHz 500 MSPS, NBSFDR, ...
Page 14
AD9911 –100 –110 75.1MHz –120 –130 100.3MHz –140 –150 40.1MHz –160 15.1MHz –170 10 100 1k 10k FREQUENCY OFFSET (Hz) Figure 19. Residual Phase Noise (SSB) with f 75.1 MHz, 100.3 MHz 500 MHz with REF_CLK Multiplier Bypassed ...
Page 15
START 0Hz 25MHz/ Figure 25. SpurKiller Disabled and Three Spurs Identified 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 25MHz/ Figure ...
Page 16
AD9911 1 CH1 100mVΩ M50.0ns Figure 31. Primary Channel (62 MHz) 100% Amplitude Modulated by CH0 (4 MHz) CH1 –4mV Rev Page ...
Page 17
APPLICATION CIRCUITS REFERENCE Figure 32. DDS in PLL Feedback Locking to Reference Offering Fine Frequency and Delay Adjust Tuning CENTRAL CONTROL Figure 33. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference ...
Page 18
AD9911 THEORY OF OPERATION PRIMARY DDS CORE The AD9911 has one complete DDS (Channel 1) that consists of a 32-bit phase accumulator, a phase-to-amplitude converter, and 10-bit DAC. Together, these digital blocks generate a sine wave when the phase accumulator ...
Page 19
MODES OF OPERATION SINGLE-TONE MODE To configure the AD9911 in single-tone mode, the auxiliary DDS cores (CH0, CH2, and CH3) must be disabled by using the channel enable bits and digital powering down (CSR bit <7>) the three auxiliary DDS ...
Page 20
AD9911 TEST-TONE MODE Test-tone mode enables sinusoidal amplitude modulation of the carrier (CH1). Setting Bit 2 in Register 0x01 enables test-tone mode. Auxiliary CH2 and CH3 should both be disabled using the channel enable bits (CSR Bit <7>). The frequency ...
Page 21
Table 4. CLK_MODE_SEL Pin 24 FR1 <22:18> PLL, Bits = M High = 1.8 V Logic 4 ≤ M ≤ 20 High = 1.8 V Logic M < > 20 Low 4 ≤ M ≤ 20 Low ...
Page 22
AD9911 modulating phase or amplitude, the word value must be MSB- aligned in the profile registers; excess bits are ignored. In modulation mode, bits CFR <23:22> and FR1 <9:8> configure the modulation type and level. See Table 6 and Table ...
Page 23
Table 13. 2-Level Modulation—RU/RD Profile Pin Config. Bits FR1<14:12> N CH1 8-Level Modulation Using a Profile Pin for RU/RD When the RU/RD bits = 10, Profile Pin P3 is available for RU/RD. Note ...
Page 24
AD9911 FREQ SWEEP EN MUX 0 CTW0 Setting the Rate of the Linear Sweep The rate of the linear sweep is set by the intermediate step size (delta-tuning word) between S0 and E0 (see Figure 42) and the time spent ...
Page 25
See Figure 43 for the linear sweep circuitry. Figure 45 depicts a frequency sweep with no-dwell mode disabled. In this mode, the output follows the state of the profile ...
Page 26
AD9911 f OUT FTW1 FTW0 SINGLE–TONE MODE PS<1> SWEEP AND PHASE ACCUMULATOR CLEARING FUNCTIONS The AD9911 provides two different clearing functions. The first function is a continuous zeroing of the sweep logic and phase accumulator (clear and hold). ...
Page 27
DDS CORE COS(X) 10 LINEAR SWEEP ACCUMULATOR PROFILE REGISTERS 10 FOR ASK MODULATION 10 TEST TONE MODULATION AMPLITUDE SCALE FACTOR REGISTER (ACR) <0:9> MANUAL RAMP UP/DOWN (RU/RD) Ramp Rate Timer The ramp rate timer is a loadable 8-bit down counter. ...
Page 28
AD9911 SYNCHRONIZING MULTIPLE AD9911 DEVICES The AD9911 allows easy synchronization of multiple AD9911 devices. At power-up, the phase of SYNC_CLK may be offset between multiple devices. There are three options (one automatic mode and two manual modes) to compensate for ...
Page 29
I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK RELATIONSHIPS I/O_UPDATE and SYNC_CLK are used together to transfer data from the I/O buffer to the active registers in the device. Data in the I/O buffer is inactive. SYNC_CLK is a rising edge active signal. ...
Page 30
AD9911 I/O PORT OVERVIEW The AD9911 I/O port offers multiple configurations to provide significant flexibility. The I/O port includes an SPI-compatible mode of operation. Flexibility is provided by four data (SDIO_0:3) pins supporting four programmable modes of I/O operation. Three ...
Page 31
Bit 7 of the instruction byte (R/Wb) determines whether a read or write data transfer occurs after the instruction byte write. set indicates a read operation; Cleared indicates a write operation. Bit 4 to Bit 0 of the instruction byte ...
Page 32
AD9911 Single-Bit Serial (2- and 3-Wire) Modes The single-bit serial mode interface allows read/write access to all registers that configure the AD9911. MSB-first or LSB-first transfer formats and the SYNC_I/O function are supported. In 2-wire mode, the SDIO_0 pin is ...
Page 33
SCLK SDIO_3 SDIO_2 SDIO_1 SDIO_0 INSTRUCTION CYCLE CS SCLK SDIO_0 (I0) (I1) (I2) (I3) Figure 53. Single-Bit Serial Mode (2-Wire) Read Timing—Clock Stall High INSTRUCTION CYCLE CS SCLK SDIO_0 (I0) (I1) (I2) ...
Page 34
AD9911 CS SCLK SDIO_1 SDIO_0 SCLK SDIO_3 SDIO_2 SDIO_1 SDIO_0 INSTRUCTION CYCLE DATA TRANSFER CYCLE (D1) (I1) (I3) (I5) (I7 (I0) (I2) (I4) (I6) (D0) Figure 55. 2-Bit Mode Read ...
Page 35
REGISTER MAPS CONTROL REGISTER MAP Table 24. Register Name Bit (Address) Range Bit 7 (MSB) Bit 6 Channel <7:0> Auxiliary Auxiliary Select Channel 3 Channel 2 1 Register (W/R enable ) (W/R enable (CSR) (0x00) Function <7:0> Reference clock External ...
Page 36
AD9911 CHANNEL REGISTER MAP Table 25. Register Name Bit (Address) Range Bit 7 (MSB) Channel <7:0> Digital power- 1 Function (CFR) down (0x03) <15:8> Linear sweep no-dwell <23:16> Amplitude frequency phase select <23:22> Channel <7:0> Frequency Tuning <15:8> 1 Word ...
Page 37
PROFILE REGISTER MAP Table 26. Bit Register Name (address) Range Channel Word 1 (CTW1) (0x0A) <31:0> Channel Word 2 (CTW2) (0x0B) <31:0> Channel Word 3 (CTW3) (0x0C) <31:0> Channel Word 4 (CTW4) (0x0D) <31:0> Channel Word 5 (CTW5) (0x0E) <31:0> ...
Page 38
AD9911 CONTROL REGISTER DESCRIPTIONS CHANNEL SELECT REGISTER (CSR) The CSR register determines if channels are enabled or disabled by the status of the channel enable bits. Channels are enabled by default. The CSR register also determines which mode and format ...
Page 39
FR1 <12:14> profile pin configuration bits. The profile pin configuration bits assign the profile and SDIO pins for the different tasks. See the Shift Keying Modulation section for examples. FR1 <15> inactive. FR1 <17:16> charge pump current control. FR1 <17:16> ...
Page 40
AD9911 CFR <6> (default). The DAC is enabled for operation. CFR <6> The DAC is disabled and held in its lowest power dissipation state. CFR <7> digital power-down. CFR <7> (default). The digital core ...
Page 41
OUTLINE DIMENSIONS BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9911BCPZ –40°C to +85°C 1 AD9911BCPZ-REEL7 –40°C to +85°C AD9911/PCB Pb-free part. 8.00 0.60 MAX 0.60 MAX ...
Page 42
AD9911 NOTES Rev Page ...
Page 43
NOTES Rev Page AD9911 ...
Page 44
AD9911 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05785-0-5/06(0) Rev Page ...