KIT EVAL FOR CP2201 ETH CTRLR

CP2201EK

Manufacturer Part NumberCP2201EK
DescriptionKIT EVAL FOR CP2201 ETH CTRLR
ManufacturerSilicon Laboratories Inc
TypeControllers & Processors
CP2201EK datasheets
 

Specifications of CP2201EK

Main PurposeInterface, Ethernet SensorEmbeddedYes, MCU, 8-Bit
Utilized Ic / PartCP2200, CP2201Primary AttributesTemperature and Light Sensor
Secondary AttributesGraphic User InterfaceInterface TypeEthernet
ProductModulesSilicon ManufacturerSilicon Labs
Silicon Core NumberCP2201Silicon Family NameCP220x
Kit ContentsCP2201 Evaluation Board, Power Adapter, CAT5e Ethernet Cable, CD-ROM, Quick-Start GuideFor Use With/related ProductsCP2201
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names336-1316
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Download datasheet (2Mb)Embed
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S
- C
E
I N G L E
H I P
T H E R N E T
Ethernet Controller
Integrated IEEE 802.3 MAC and 10 BASE-T PHY
Fully compatible with 100/1000 BASE-T networks
Full/Half duplex with auto-negotiation
Automatic polarity detection and correction
Automatic retransmission on collision
Automatic padding and CRC generation
Supports broadcast and multi-cast MAC addressing
Parallel Host Interface (30 Mbps Transfer Rate)
8-bit multiplexed or non-multiplexed mode
Only 11 I/O pins required in multiplexed mode
®
®
Intel
or Motorola
Bus Format
Interrupt on received packets and Wake-on-LAN
8 kB Flash Memory
8192 bytes ISP non-volatile memory
Factory pre-programmed unique 48-bit MAC Address
No external EEPROM required
Other Features
LED output drivers (Link/Activity)
Dedicated 2 kB RAM transmit buffer and 4 kB RAM
receive FIFO buffer
Power-on Reset
5 V Tolerant I/O
CP2200
Host
Interface
Rev. 1.0 5/07
C
O N T R O L L E R
Software Support
Royalty-free TCP/IP stack with device drivers
TCP/IP Stack Configuration Wizard
Hardware diagnostic software and example code
Example Applications
Remote sensing and monitoring
Inventory management
VoIP phone adapters
Point-of-sale devices
Network clocks
Embedded Web Server
Remote Ethernet-to-UART bridge
Supply Voltage
3.1 to 3.6 V
Package
Pb-free 48-pin TQFP (9x9 mm footprint)
Pb-free 28-pin QFN (5x5 mm footprint)
Ordering Part Number
CP2200-GQ (48-pin)
CP2201-GM (28-pin)
Temperature Range: –40 to +85 °C
20 MHz
XTAL
LED
8 kB
Clock
Control
Flash
2 kB
Tx Buffer
Ethernet
Ethernet
MAC
PHY
4 kB
Rx FIFO
Figure 1. Example System Diagram
Copyright © 2007 by Silicon Laboratories
C P 2 2 0 0 / 1
ACT
LED
TX+/TX-
RJ-45
RX+/RX-
LINK
LED
CP2200/1

CP2201EK Summary of contents

  • Page 1

    Ethernet Controller Integrated IEEE 802.3 MAC and 10 BASE-T PHY Fully compatible with 100/1000 BASE-T networks Full/Half duplex with auto-negotiation Automatic ...

  • Page 2

    CP2200/1 2 Rev. 1.0 ...

  • Page 3

    T C ABLE OF ONTENTS Section 1. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    CP2200/1 12.5. Receive Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    System Overview The CP2200 single-chip Ethernet controller containing an integrated IEEE 802.3 Ethernet Media Access Controller (MAC), 10BASE-T Physical Layer (PHY), and 8 kB Non-Volatile Flash Memory available in a compact QFN-28 package ...

  • Page 6

    CP2200/1 2. Typical Connection Diagram Figure 2 and Figure 3 show typical connection diagrams for the 48-pin CP2200 and 28-pin CP2201. 0.1 uF 0.1 uF XTAL1 10 MΩ 20 MHz XTAL2 MCU Optional A15 CS 8 ...

  • Page 7

    XTAL1 10 MΩ 20 MHz XTAL2 MCU 8 AD[7:0] AD[7: ALE ALE Optional INT INT DGND1 DGND2 GND AGND Note: The CP220x should be placed within 1 ...

  • Page 8

    CP2200/1 3. Absolute Maximum Ratings Table 1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum Total current through ...

  • Page 9

    Electrical Characteristics Table 2. Global DC Electrical Characteristics V = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter Supply Voltage Supply Current in Normal Mode (Transmitting) Supply Current in Normal Mode (No Network Traffic) ...

  • Page 10

    CP2200/1 5. Pinout and Package Definitions Name Pin Numbers 48-pin 28-pin AV Power In 3.1–3.6 V Analog Power Supply Voltage Input. AGND Power In 3.1–3.6 V Digital Power Supply Voltage Input. DD1 DGND1 ...

  • Page 11

    Table 4. CP2200/1 Pin Definitions (Continued) Name Pin Numbers 48-pin 28-pin RD/(DS WR/(R/ D0/AD0 16 11 D1/AD1 17 12 D2/AD2 18 13 D3/AD3 19 14 D4/AD4 20 15 D5/AD5 21 16 D6/AD6 22 ...

  • Page 12

    CP2200 ACT 2 LINK 3 AGND 4 AV+ 5 RX TX Figure 4. 48-pin TQFP Pinout Diagram 12 CP2200 Top View Rev. 1 ...

  • Page 13

    PIN 1 IDENTIFIER Figure 5. 48-pin TQFP Package Dimensions Table 5. TQFP-48 Package Rev. 1.0 CP2200/1 Dimensions MM Min Typ ...

  • Page 14

    CP2200/1 GND LA 1 AGND 2 AV+ 3 RX- 4 RX+ 5 TX+ 6 TX- 7 Figure 6. QFN-28 Pinout Diagram (Top View) 14 CP2201 Top View GND Rev. 1.0 21 ALE/(AS) 20 DGND2 19 VDD2 18 AD7 17 AD6 ...

  • Page 15

    Bottom View DETAIL Side View e DETAIL Figure 7. QFN-28 Package Drawing Table 6. QFN-28 Package Dimensions 15 Min A 0.80 16 ...

  • Page 16

    CP2200/1 0.50 mm 0.20 mm Optional GND Connection L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 8. Typical QFN-28 Landing Diagram 16 Top View E2 E Rev. 1.0 0.85 mm ...

  • Page 17

    L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 9. Typical QFN-28 Solder Paste Diagram Top View 0.60 mm 0.30 mm 0. ...

  • Page 18

    CP2200/1 6. Functional Description 6.1. Overview In most systems, the CP2200/1 is used for transmitting and receiving Ethernet packets, non-volatile data storage, and controlling Link and Activity LEDs. The device is controlled using direct and indirect internal registers accessible through ...

  • Page 19

    Clocking Options The CP2200/1 can be clocked from an external parallel-mode crystal oscillator or CMOS clock. Figure 10 and Figure 11 show typical connections for both clock source types crystal oscillator is chosen to clock the device, ...

  • Page 20

    CP2200/1 Table 7. Clocking Requirements V = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Frequency Frequency Error Duty Cycle Table 8. Input Clock Pin (XTAL1) DC Electrical Characteristics V = 3.1 to 3.6 V, ...

  • Page 21

    LED Control The CP2200/1 can be used to control link status and activity LEDs. The CP2200 (48-pin TQFP) has two push-pull LED drivers that can source each. The CP2201 (28-pin QFN) has a single push-pull ...

  • Page 22

    CP2200/1 6.6. Sending and Receiving Packets After reset initialization is complete, the CP2200/1 is ready to send and receive packets. Packets are sent by loading data into the transmit buffer using the AutoWrite register and writing ‘1’ to TXGO. See ...

  • Page 23

    Internal Memory and Registers The CP2200/1 is controlled through direct and indirect registers accessible through the parallel host interface. The host interface provides an 8-bit address space, of which there are 114 valid direct register locations (see Table 11 ...

  • Page 24

    CP2200/1 Register 1. RAMADDRH: RAM Address Pointer High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: RAMADDRH: RAM Address Register High Byte Holds the most significant eight bits of the target RAM address. Register 2. RAMADDRL: RAM Address Pointer Low ...

  • Page 25

    Internal Registers The CP2200/1 has 114 direct internal registers and 9 indirect registers. The registers are grouped into ten categories based on function. Table 10 lists the register groups and provides links to the detailed register descriptions for each ...

  • Page 26

    CP2200/1 Register Address INT0 0x63 INT0EN 0x64 INT0RD 0x76 INT1 0x7F INT1EN 0x7D INT1RD 0x7E IOPWR 0x70 MACADDR 0x0A MACDATAH 0x0B MACDATAL 0x0C MACRW 0x0D OSCPWR 0x7C PHYCF 0x79 PHYCN 0x78 PHYSTA 0x80 RAMADDRH 0x08 RAMADDRL 0x09 RAMRXDATA 0x02 RAMTXDATA ...

  • Page 27

    Table 11. Direct Registers Register Address RXHASHH 0x0E RXHASHL 0x0F RXSTA 0x12 SWRST 0x75 TLB0ADDRH 0x27 TLB0ADDRL 0x28 TLB0INFOH 0x23 TLB0INFOL 0x24 TLB0LENH 0x25 TLB0LENL 0x26 TLB1ADDRH 0x2D TLB1ADDRL 0x2E TLB1INFOH 0x29 TLB1INFOL 0x2A TLB1LENH 0x2b TLB1LENL 0x2C TLB2ADDRH 0x33 ...

  • Page 28

    CP2200/1 Register Address TLB4ADDRL 0x40 TLB4INFOH 0x3B TLB4INFOL 0x3C TLB4LENH 0x3D TLB4LENL 0x3E TLB5ADDRH 0x45 TLB5ADDRL 0x46 TLB5INFOH 0x41 TLB5INFOL 0x42 TLB5LENH 0x43 TLB5LENL 0x44 TLB6ADDRH 0x4B TLB6ADDRL 0x4C TLB6INFOH 0x47 TLB6INFOL 0x48 TLB6LENH 0x49 TLB6LENL 0x4A TLB7ADDRH 0x51 TLB7ADDRL ...

  • Page 29

    Table 11. Direct Registers Register Address TXPAUSEH 0x55 TXPAUSEL 0x56 TXPWR 0x7A TXSTA0 0x62 TXSTA1 0x61 TXSTA2 0x60 TXSTA3 0x5F TXSTA4 0x5E TXSTA5 0x5D TXSTA6 0x5C TXSTARTH 0x59 TXSTARTL 0x5A VDMCN 0x13 Description Transmit Pause High Byte Transmit Pause Low ...

  • Page 30

    CP2200/1 8. Interrupt Sources The CP2200/1 can alert the host processor when any of the 14 interrupt source events listed in Table 12 triggers an interrupt. The CP2200/1 alerts the host by setting the appropriate flags in the interrupt status ...

  • Page 31

    Register 5. INT0: Interrupt Status Register 0 (Self-Clearing EOPINT RXEINT SELFINT OSCINT FLWEINT Bit7 Bit6 Bit5 Note: Reading this register will clear all INT0 interrupt flags. Bit 7: EOPINT: End of Packet Interrupt Flag 0: The last ...

  • Page 32

    CP2200/1 Register 6. INT0RD: Interrupt Status Register 0 (Read-Only EOPINTR RXEINTR SELFINTR OSCINTR FLWEINTR TXINTR RXFINTR RXINTR 00000000 Bit7 Bit6 Bit5 Note: Reading this register will not clear INT0 interrupt flags. Bit 7: EOPINTR: End of Packet ...

  • Page 33

    Register 7. INT0EN: Interrupt Enable Register 0 R/W R/W R/W EEOPINT ERXEINT ESELFINT EOSCINT EFLWEINT ETXINT Bit7 Bit6 Bit5 Bit 7: EEOPINT: Enable End of Packet Interrupt 0: Disable End of Packet Interrupt. 1: Enable End of Packet Interrupt. Bit ...

  • Page 34

    CP2200/1 Register 8. INT1: Interrupt Status Register 1 (Self-Clearing) R/W R/W RC — — WAKEINT LINKINT Bit7 Bit6 Bit5 Note: Reading this register will clear all INT1 interrupt flags. Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit ...

  • Page 35

    Register 9. INT1RD: Interrupt Status Register 1 (Read-Only) R/W R/W R — — WAKEINTR LINKINTR JABINTR ANFINTR Reserved ANCINTR 00000000 Bit7 Bit6 Bit5 Note: Reading this register will not clear INT1 interrupt flags. Bits 7–6: UNUSED. Read = 00b, Write ...

  • Page 36

    CP2200/1 Register 10. INT1EN: Interrupt Enable Register 1 R/W R/W R/W — — EWAKEINT ELINKINT EJABINT EANFINT Reserved EANCINT 00000000 Bit7 Bit6 Bit5 Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: EWAKEINT: Enable “Wake-on-Lan” Interrupt 0: ...

  • Page 37

    Reset Sources Reset circuitry allows the CP2200 easily placed in a predefined default condition. Upon entry to this reset state, the following events occur: All direct and indirect registers are initialized to their defined reset values. Digital ...

  • Page 38

    CP2200/1 9.1. Power-On Reset During power-up, the CP2200/1 is held in the reset state, and the /RST pin is driven low until delay (T ) occurs between the time V RST PORDelay reset; the typical delay ...

  • Page 39

    Power-fail When a power-down transition or power irregularity causes V drive the /RST pin low and return the CP2200/1 to the reset state. When V CP2200/1 will be released from the reset state as shown in Figure 14. The ...

  • Page 40

    CP2200/1 9.5. Software Reset The software reset provides the host CPU the ability to reset the CP2200/1 through the parallel host interface. Writing a ‘1’ to RESET (SWRST.2) will force the device to enter the reset state with the exception ...

  • Page 41

    Determining the Source of the Last Reset The RSTSTA register can be used to determine the cause of the last reset. Note: If the PORSI bit is set to logic 1, all other bits in RSTSTA are undefined. It ...

  • Page 42

    CP2200/1 9.7. De-Selecting Interrupt Sources The power-fail (V Monitor) reset is automatically enabled after every power-on reset. The software reset is DD enabled after every device reset, regardless of the reset source. The RSTEN register can be used to prevent ...

  • Page 43

    Power Modes The CP2200/1 has four power modes that can be used to minimize overall system power consumption. The power modes vary in device functionality and recovery methods. Each of the following power modes is explained in the following ...

  • Page 44

    CP2200/1 10.1. Normal Mode Normal Mode should is used whenever the host is sending or receiving packets. In this mode, the CP2200/01 is fully functional. Typical Normal Mode power consumption is listed in Table 2 on page 9. Note: When ...

  • Page 45

    Disabling Secondary Device Functions The LED Drivers, weak pull-ups, and V supply current for the V Monitor is specified in Table 13 on page 42. Disabling weak pull-ups will save current if DD the MOTEN and MUXEN pins are ...

  • Page 46

    CP2200/1 Register 16. OSCPWR: Oscillator Power Register R/W R/W R/W — — — Bit7 Bit6 Bit5 Bits 7–5: UNUSED. Read = 0000b, Write = don’t care. Bit 4–2: RESERVED. Read = 100b; Must write x00b. Bit 1: UNUSED. Read = ...

  • Page 47

    Transmit Interface 11.1. Overview The CP2200/1 provides a simple interface for transmitting Ethernet packets requiring the host to only load the source and destination addresses, length/type, and data into the transmit buffer. All other IEEE 802.3 requirements, such as ...

  • Page 48

    CP2200/1 11.2. Transmitting a Packet Once reset initialization is complete (See ), the CP2200/1 is ready to transmit Ethernet packets. The following procedure can be used to transmit a packet: Step 1: Wait for the previous packet to complete (TXBUSY ...

  • Page 49

    Transmit Status and Control Registers The CP2200 transmit interface is controlled and managed through the registers in Table 14. After each packet is transmitted, information about the last transmitted packet can be obtained from the 52-bit transmit status vector ...

  • Page 50

    CP2200/1 Table 15. Transmit Status Vector Description Bit Field Name 51 Transmitted VLAN Frame 50 Back Pressure Applied 49 Transmitted PAUSE Frame 48 Transmitted Control Frame 47-32 Total Bytes Transmitted 31 Transmit Under-Run 30 Jumbo Packet Detected 29 Late Collision ...

  • Page 51

    Register 18. TXCN: Transmit Control Register R/W R/W R/W OVRRIDE — CRCENOV PADENOV TXPPKT BCKPRES FDPLXOV Bit7 Bit6 Bit5 Bit 7: OVRRIDE: Default Override 0: Settings for bits and 1 in TXCN will be ignored. MAC ...

  • Page 52

    CP2200/1 Register 20. TXPAUSEH: Transmit Pause High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TXPAUSEH: Transmit Pause High Byte High byte of the 16-bit pause value sent in a PAUSE control packet. The pause value is in units ...

  • Page 53

    Register 24. TXENDH: Transmit Data Ending Address High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TXENDH: Transmit Data Ending Address High Byte High byte of the address of the last byte added to the transmit buffer. Register 25. ...

  • Page 54

    CP2200/1 Register 27. TXSTA6: Transmit Status Vector 6 R/W R/W R/W — — — Bit7 Bit6 Bit5 Note: This register contains bits 51–48 of the Transmit Status Vector. Bits 7–4: UNUSED. Read = 0000b, Write = don’t care. Bit 3. ...

  • Page 55

    Register 29. TXSTA4: Transmit Status Vector Bit7 Bit6 Bit5 Note: This register contains bits 40-32 of the Transmit Status Vector. Bits 7-0: TXSTA4: Total Bytes Transmitted Low Byte The least significant 8-bits of the total number ...

  • Page 56

    CP2200/1 Register 31. TXSTA2: Transmit Status Vector TXOK TXTYPE TXLCERR TXCRCER TXCOL3 Bit7 Bit6 Bit5 Note: This register contains bits 23–16 of the Transmit Status Vector. Bit 7: TXOK: Transmit Successful 0: Transmission was aborted. 1: ...

  • Page 57

    Register 33. TXSTA0: Transmit Status Vector Bit7 Bit6 Bit5 Note: This register contains bits 15–8 of the Transmit Status Vector. Bits 7–0: TXSTA0: Transmit Byte Count Low Byte The least significant 8-bits of the number of ...

  • Page 58

    CP2200/1 12. Receive Interface 12.1. Overview The CP2200/1 has a 4k circular receive FIFO buffer and an 8 entry translation look-aside buffer (TLB) capable of storing packets at a time. Each TLB entry holds the starting address, ...

  • Page 59

    Note: The value of CPADDRH:CPADDRL may be invalid if an overflow event occurs. After an overflow, the FIFOHEADH:FIFO- HEADL pointer should be used to determine the starting address of the current packet. CPLEN will always remain valid even after an ...

  • Page 60

    CP2200/1 12.5. Receive Status and Control Registers The CP2200/1 receive interface is controlled and managed through the registers in Table 16. The current packet registers provide information about the next packet to be unloaded from the receive buffer (the oldest ...

  • Page 61

    Register 34. RXCN: Receive Interface Control R/W R/W R/W — — — Bit7 Bit6 Bit5 Bits 7–4: UNUSED. Read = 0000b, Write = don’t care. Bit 3: RXINH: Receive Inhibit Setting this bit to ‘1’ temporarily inhibits new packet reception. ...

  • Page 62

    CP2200/1 Register 36. RXAUTORD: Receive AutoRead Data Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: RXAUTORD: Receive AutoRead Data Register Reads from this register read a single byte from the receive buffer and adjust the receive buffer pointer RXFIFOHEAD ...

  • Page 63

    Register 39. RXHASHL: Multicast Hash Table Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: RXHASHL: Multicast Hash Table Low Byte Low Byte of 16-bit multicast hash table. Register 40. CPINFOH: Current Packet Information High Byte ...

  • Page 64

    CP2200/1 Register 41. CPINFOL: Current Packet Information Low Byte RXOK LENGTH LENERR CRCERR Reserved Reserved Bit7 Bit6 Bit5 Bit 7: RXOK: Receive OK 0: Receive not OK. 1: Receive OK. Bit 6: LENGTH: Length/Type Field Detection 0: ...

  • Page 65

    Register 44. CPADDRH: Current Packet Address High Byte Bit7 Bit6 Bit5 Note: The contents of this register are invalid following a buffer overflow event. Bits 7–0: CPADDRH: Current Packet Address High Byte High byte of the current ...

  • Page 66

    CP2200/1 12.6. Advanced Receive Buffer Operation Receive buffer operation is automatically handled by hardware and does not require any assistance from the host processor. Note: The information in this section is provided for reference purposes only and will typically not ...

  • Page 67

    The Receive FIFO Full interrupt will be generated once all free space in the buffer is used or all TLB slots are filled. The host processor should read the RXFIFOSTA register to determine the cause of the interrupt. To receive ...

  • Page 68

    CP2200/1 Register 47. TLBVALID: TLB Valid Indicator R/W R/W R/W VAL7 VAL6 VAL5 Bit7 Bit6 Bit5 Bits 7–0: TLBVALID: TLB Valid Indicator Displays the valid bits for the eight TLB slots in a single byte. Note: This register may be ...

  • Page 69

    Register 49. TLBnINFOL: TLBn Information Low Byte RXOK LENGTH LENERR CRCERR Reserved Reserved Bit7 Bit6 Bit5 Address: TLB0INFOH: 0x24; TLB1INFOH: 0x2A; TLB2INFOH: 0x30; TLB3INFOH: 0x36; TLB4INFOH: 0x3C; TLB5INFOH: 0x42; TLB6INFOH: 0x48; TLB7INFOH: 0x4E Bit 7: RXOK: Receive ...

  • Page 70

    CP2200/1 Register 51. TLBnLENL: TLBn Packet Length Low Byte Bit7 Bit6 Bit5 Address: TLB0LENH: 0x26; TLB1LENH: 0x2C; TLB2LENH: 0x32; TLB3LENH: 0x38; TLB4LENH: 0x3E; TLB5LENH: 0x44; TLB6LENH: 0x4A; TLB7LENH: 0x50 Bits 7–0: TLBnLENL: TLBn Packet Length Low Byte ...

  • Page 71

    Register 54. RXFIFOHEADH: Receive FIFO Head Pointer High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: RXFIFOHEADH: Receive FIFO Head Pointer High Byte High byte of the receive FIFO buffer head pointer. Register 55. RXFIFOHEADL: Receive FIFO Head Pointer ...

  • Page 72

    CP2200/1 Register 58. RXFIFOSTA: Receive FIFO Status Register R/W R/W R/W — — — Bit7 Bit6 Bit5 This register is set by hardware and is valid after an RX FIFO Full Interrupt is generated or if TLBVALID equals 0xFF. Bits ...

  • Page 73

    Flash Memory The CP2200/1 has on-chip non-volatile Flash memory fully accessible by the host processor. The last six bytes of this memory space (addresses 0x1FFA to 0x1FFF) are factory preprogrammed and contain a unique 48- bit ...

  • Page 74

    CP2200/1 13.2. Reading the Flash Memory Flash reads occur much faster than Flash write or erase operations and are completed within the minimum read strobe time specified by the parallel host interface. Flash is read using the FLASHADDRH:FLASHADDRL, FLASHDATA, and ...

  • Page 75

    Flash Access Registers The CP2200 Flash is accessed through the registers in Table 17. See the register tables following Table 17 for detailed register descriptions Table 19. Flash Access Register Summary Register Long Name FLASHSTA Flash Status FLASHKEY Flash ...

  • Page 76

    CP2200/1 Register 60. FLASHKEY: FLASH Lock and Key Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: FLKEY: Flash Lock and Key Register This register must be written to unlock the Flash for writing or erasing. To unlock the Flash, ...

  • Page 77

    Register 63. FLASHDATA: FLASH Read/Write Data Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: FLASHDATA: Flash Read/Write Data Register Read: Value of the Flash byte at the location specified by FLASHADDRH:FLASHADDRL. Write: Initiates a Flash write operation to the Flash ...

  • Page 78

    CP2200/1 14. Media Access Controller (MAC) The CP2200/1 has an IEEE 802.3 compliant Ethernet Media Access Controller (MAC). The MAC can be configured to automatically pad short frames (full duplex mode only), append CRC, and perform frame length checking. A ...

  • Page 79

    Register 66. MACADDR: MAC Indirect Address R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: MACADDR: MAC Indirect Address Indirect MAC register address targeted by reads/writes to MACRW. Register 67. MACDATAH: MAC Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 ...

  • Page 80

    CP2200/1 14.3. Indirect MAC Register Descriptions The MAC is configured through nine indirect 16-bit registers listed in Table 20. See the figures following Table 20 for detailed register descriptions. Table 20. Indirect MAC Register Summary Register Long Name MACCN MAC ...

  • Page 81

    Indirect Register 1. MACCN: MAC Control Register R/W R/W R/W Reserved RANDRST Bit15 Bit14 Bit13 R/W R/W R/W Reserved LOOPBCK TXPAUSE RXPAUSE Reserved Bit7 Bit6 Bit5 Bit 15: Reserved. Read = varies; Must write 0b. Bit 14: RANDRST: Random Number ...

  • Page 82

    CP2200/1 Indirect Register 2. MACCF: MAC Configuration Register R/W R/W R/W Reserved ABORTD EBBPD Bit15 Bit14 Bit13 R/W R/W R/W PADMD1 PADMD0 PADEN Bit7 Bit6 Bit5 Bit 15: Reserved. Read = 0b; Must write 0b. Bit 14: ABORTD: Abort Disable ...

  • Page 83

    Indirect Register 2. MACCF: MAC Configuration Register (Continued) PADMD1[7] PADMD0[6] PADEN[5] CRCEN[ Bit 3: PHEADER: Proprietary Header Select Bit 0: No proprietary header exists on the front of IEEE 802.3 ...

  • Page 84

    CP2200/1 Indirect Register 3. IPGT: Back-to-Back Inter-Packet Gap Register R/W R/W R/W Bit15 Bit14 Bit13 R/W R/W R/W Reserved Bit7 Bit6 Bit5 Bits 15–7:Reserved. Read = 000000000b; Must write 000000000b. Bits 6–0: IPGT: Back-to-Back Inter-Packet Gap Register Sets the minimum ...

  • Page 85

    Indirect Register 5. CWMAXR: Collision Window and Maximum Retransmit Register R/W R/W R/W Reserved Bit15 Bit14 Bit13 R/W R/W R/W Reserved Bit7 Bit6 Bit5 Note: This register does not require initialization and will be left at its reset value by ...

  • Page 86

    CP2200/1 Indirect Register 7. MACAD0: MAC Address 0 R/W R/W R/W Bit15 Bit14 Bit13 R/W R/W R/W Bit7 Bit6 Bit5 Bits 15–8:OCTET6: MAC Address, 6th Octet This field holds the sixth (least significant) octet of the MAC address. Bits 7–0: ...

  • Page 87

    Indirect Register 9. MACAD2: MAC Address 2 R/W R/W R/W Bit15 Bit14 Bit13 R/W R/W R/W Bit7 Bit6 Bit5 Bits 15–8:OCTET2: MAC Address, 2nd Octet This field holds the second octet of the MAC address. Bits 7–0: OCTET1: MAC Address, ...

  • Page 88

    CP2200/1 15. Physical Layer (PHY) The CP2200/1 has an IEEE 802.3 compliant 10 BASE-T Ethernet physical layer transceiver that includes a receiver, transmitter, auto-negotiation, loopback, jabber, smart squelch, polarity correction, and link integrity functions. If enabled, the auto-negotiation function automatically ...

  • Page 89

    Loopback Mode Loopback Mode provides the ability to transfer data from the physical layer’s output directly to it’s input to aid in system debugging. When PHYCN.3 is set to ‘1’, transmit data is looped back to the receiver via ...

  • Page 90

    CP2200/1 15.7. Initializing the Physical Layer The physical layer should be configured to the desired mode prior to setting the enable bit PHYEN (PHYCN.7). The following procedure should be used to initialize the physical layer: Step 1: If auto-negotiation is ...

  • Page 91

    Register 70. PHYCN: Physical Layer Control Register R/W R/W R/W PHYEN TXEN RXEN Bit7 Bit6 Bit5 Important Note: When using auto-negotiation, the auto-negotiation enable bit, AUTONEG (PHYCF.4), must setting PHYEN, TXEN, and RXEN restart auto-negotiation, be set ...

  • Page 92

    CP2200/1 Register 71. PHYCF: Physical Layer Configuration Register R/W R/W R/W SMSQ LINKINTG JABBER AUTONEG Reserved ADPAUSE AUTOPOL REVPOL 00000000 Bit7 Bit6 Bit5 Bit 7: SMSQ: Receiver Smart Squelch Enable Bit 0: Receiver Smart Squelch is disabled. 1: Receiver Smart ...

  • Page 93

    Register 72. PHYSTA: Physical Layer Status Register LGCILF LGCLSF AKDLF Bit7 Bit6 Bit5 Note: The Auto-Negotiation states and error types are described in Clause 28 of IEEE 802.3. Bit 7: LGCILF: Link Good Check Incompatible Link Failure ...

  • Page 94

    CP2200/1 Table 23. 10BASE-T Transmit Switching Characteristics V = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Symbol TX Pair Jitter into 100 Ω Load T TXJIT T TX Pair Positive Hold time at End of ...

  • Page 95

    Transmit Link Integrity ± TX Receive Link Integrity LINK (LED Driver) ± RX Table 25. 10BASE-T Link Integrity Switching Characteristics V = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Symbol T First Transmitted Link Pulse ...

  • Page 96

    CP2200/1 16. Parallel Interface The CP2200/1 has an 8-bit parallel host interface used to access the direct registers on the device. The parallel interface supports multiplexed or non-multiplexed operation using the Intel pin can be driven high to place the ...

  • Page 97

    Figure 23. Nonmuxed Intel WRITE Table 26. Non-Multiplexed Intel Mode AC Parameters Symbol Description T Address Setup Time (Read/Write Low Pulse Width (Read Falling to Valid Data Out (Read) VD1 T RD Rising to ...

  • Page 98

    CP2200/1 16.2. Multiplexed Intel Format ALE AD[7:0] RD Notes must be asserted with or before RD must remain de-asserted during a READ. ALE AD[7:0] WR Notes must be asserted with or before WR 2. ...

  • Page 99

    Table 27. Multiplexed Intel Mode AC Parameters Parameter Description T ALE High Pulse Width ALE1 T ALE Falling to RD/WR Falling ALE2 T Address Setup Time (Read/Write Address Hold Time (Read/Write Low Pulse Width RD ...

  • Page 100

    CP2200/1 16.3. Non-Multiplexed Motorola Format A[7:0] /DS D[7:0] R/W Note: /CS must be asserted with or before /DS. Figure 26. Nonmuxed Motorola READ A[7:0] /DS D[7:0] R/W Note: /CS must be asserted with or before /DS. Figure 27. Nonmuxed Motorola ...

  • Page 101

    Table 28. Non-Multiplexed Motorola Mode AC Parameters Parameter Description T Address Setup Time (Read/Write R/W Setup Time (Read/Write) RWS T DS Low Pulse Width (Read) DSR T DS Falling to Valid Data Out (Read) VD1 T DS Rising ...

  • Page 102

    CP2200/1 16.4. Multiplexed Motorola Format AS AD[7:0] /DS R/W Note: /CS must be asserted with or before /DS. Figure 28. Multiplexed Motorola READ AS AD[7:0] /DS R/W Note: /CS must be asserted with or before /DS. Figure 29. Multiplexed Motorola ...

  • Page 103

    Table 29. Multiplexed Motorola Mode AC Parameters Parameter Description T AS High Pulse Width (Read/Write) AS1 T AS Falling to DS Falling (Read/Write) AS2 T Address Setup Time (Read/Write Address Hold Time (Read/Write R/W Setup Time ...

  • Page 104

    CP2200/1 17. Revision-Specific Behavior This chapter contains behavioral differences between CP220x "REV C" and behavior as stated in the data sheet. 17.1. Revision Identification The Lot ID Code on the top side of the device package can be used for ...

  • Page 105

    MAC Address Filtering Problem For unicast packets received over the Ethernet wire, the receive filter only validates the first 5 bytes of the 6-byte Ethernet MAC Address. Any packet addressed to a device whose MAC address only differs in ...

  • Page 106

    CP2200 OCUMENT HANGE IST Revision 0.4 to Revision 0.41 Modified Figure 2, “Typical Connection Diagram (Non-Multiplexed),” on page 6 and Figure 3, “Typical Connection Diagram (Multiplexed),” on page 7 for improved EMI emmissions and common mode stability. ...

  • Page 107

    N : OTES Rev. 1.0 CP2200/1 107 ...

  • Page 108

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