CP2400AB Silicon Laboratories Inc, CP2400AB Datasheet

BOARD EVAL SPI LCD DRIVER CP2400

CP2400AB

Manufacturer Part Number
CP2400AB
Description
BOARD EVAL SPI LCD DRIVER CP2400
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of CP2400AB

Main Purpose
LCD Development
Embedded
No
Utilized Ic / Part
CP2400
Primary Attributes
I²C, SMBus Interfaces
Secondary Attributes
Up to 128 segments
Product
Microcontroller Accessories
Core Processor
CP2400
Clock Speed
20 MHz
Interface Type
SPI
Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Cpu Core
CP2400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
336-1857
128/64 S
LCD Driver
GPIO Expander
Real Time Clock, SmaRTClock
256 Bytes RAM
16-bit Timers
Clock Sources
Rev. 1.0 8/10
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Expands GPIO count by up to 36 pins (48-pin packages)
General purpose RAM expands the memory available to
64 segments (32-pin package)
or 20 pins (32-pin package)
GPIO pins may be configured to push-pull or open-drain
outputs with two drive levels. GPIO may also be used as
digital inputs (CP2400/1/2/3 pullups included)
Port Match Capability can wake up host controller using
interrupt pin
self-oscillate mode requires no external crystal; accepts
external 32 kHz CMOS clock
host controller.
Controls up to 128 segments (48-pin packages) or
Supports static, 2-mux, 3-mux, and 4-mux displays
On-chip bias generation with internal charge pump
Low power blink capability
5 V Tolerant I/O
Precision time keeping with 32.768 kHz watch crystal;
36-hour programmable counter with wake up alarm
Can wake up the host controller using interrupt pin
Low power (<1.5 µA)
Two general purpose 16-bit timers
20 MHz Internal oscillator
Can be clocked from an external CMOS clock
Controller
Host
EGMENT
CP2400/1/2/3
(CP2400/2)
SMBus/I2C
(CP2401/3)
Interface
Host
SPI
OR
L C D D
Copyright © 2010 by Silicon Laboratories
Oscillator
2 x 16-bit
256 Byte
20 MHz
Internal
Timers
SRAM
RIVER
Digital Bus Interface
Low Power
Example Applications
Packages
Ordering Part Numbers
Temperature Range: –40 to +85 °C
GPIO Expander
LCD Controller
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smaRTClock
2-wire SMBus/I
synchronous external clock or up to 1 Mbps with internal
clock (CP2400/2 only).
internal clock (CP2401/3 only).
device in a low power mode. SPI devices use the NSS
pin to place the device in a low power mode.
4-wire SPI Interface operates up to 2.5 Mbps with
Dedicated RST and INT pins.
Optional CLK pin can be used as a CMOS clock input.
Optional PWR pin (SMBus/I
1.8–3.6 V operation with integrated LDO
Ultra Low Power Mode w/ LCD (<3 µA typical)
Shutdown current (0.05 µA typical)
Handheld Equipment
Utility Meters
Thermostat Display
Home Security Systems
Pb-free 48-pin QFP (9x9 mm footprint) [-Q]
Pb-free 48-pin QFN (7x7 mm footprint) [-M]
Pb-free 32-pin QFN (5x5 mm footprint)
CP2400-G[M|Q] (SPI Interface)
CP2401-G[M|Q] (SMBus/I
CP2402-GM (SPI Interface)
CP2403-GM (SMBus/I
C P 2 4 0 0 / 1 / 2 / 3
2
C Interface operates up to 400 kHz with
2
C Interface)
2
C Interface)
2
32.768 kHz
C devices only) places the
Digital I/O
LCD
Optional
CP2400/1/2/3

Related parts for CP2400AB

CP2400AB Summary of contents

Page 1

S EGMENT LCD Driver Controls up to 128 segments (48-pin packages) or  64 segments (32-pin package) Supports static, 2-mux, 3-mux, and 4-mux displays  On-chip bias generation with internal charge pump  Low power blink capability  GPIO ...

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CP2400/1/2/3 2 Rev. 1.0 ...

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System Overview .................................................................................................................5 1.1. Typical Connection Diagram ..........................................................................................9 2. Absolute Maximum Ratings.............................................................................................. 11 3. Electrical Characteristics .................................................................................................. 12 4. Pinout and Package Definitions ....................................................................................... 17 5. Clocking Options ...............................................................................................................32 6. Internal Registers and Memory ........................................................................................ 34 6.1. Accessing Internal ...

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CP2400/1/2/3 15. SMBus Interface............................................................................................................... 104 15.1.Supporting Documents .............................................................................................. 104 15.2.SMBus Configuration ................................................................................................. 104 15.3.SMBus Operation....................................................................................................... 105 Document Change List ........................................................................................................ 108 Contact Information .............................................................................................................110 4 Rev. 1.0 ...

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System Overview CP2400/1/2/3 devices are fixed function LCD drivers that can also be used for expanding GPIO, timekeeping, and increasing available system RAM 256 bytes. The device is controlled using direct and indirect internal registers accessible ...

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CP2400/1/2/3 Power On Reset Reset RST Power Net VDD VREG Analog Power GND Power PWR Management SMBA0 SDA SMBus/I2C SCL (2-wire) INT Host Interface Low Power 20 MHz Oscillator External CLK CMOS Clock XTAL1 SmaRTClock Oscillator XTAL2 System Clock Configuration ...

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Power On Reset Reset RST Power Net VDD VREG Analog Digital Power Power GND Power Management SCK MISO SPI MOSI (4-wire) NSS SFR INT Bus Host Interface Low Power 20 MHz Oscillator External CLK SYSCLK CMOS Clock XTAL1 SmaRTClock Oscillator ...

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CP2400/1/2/3 Power On Reset Reset RST Power Net VDD VREG Analog Power GND Power PWR Management SMBA0 SMBA1 SDA SMBus/I2C SCL (2-wire) INT Host Interface Low Power 20 MHz Oscillator External CLK CMOS Clock XTAL1 SmaRTClock Oscillator XTAL2 System Clock ...

Page 9

Typical Connection Diagram XTAL1 32.768 kHz XTAL2 MCU SCK SCK MISO MISO MOSI MOSI NSS NSS GPIO INT GPIO RST GPIO CLK GND GND Figure 1.5. Typical Connection Diagram (SPI Interface) VDD 0 LCD0 LCDn CP240x ...

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CP2400/1/2/3 XTAL1 32.768 kHz XTAL2 VDD MCU SMBA0 SCL SCL SDA SDA GPIO INT GPIO PWR GPIO RST GPIO CLK GND GND Figure 1.6. Typical Connection Diagram (SMBus/I 10 VDD 0 LCD0 LCDn CP240x COM0 COM1 COM2 ...

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Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum Total current through V ...

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CP2400/1/2/3 3. Electrical Characteristics Table 3.1. Global Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter Supply Voltage SYSCLK T (SYSCLK High Time) SYSH T (SYSCLK Low Time) SYSL Specified Operating Temperature ...

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Table 3.2. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Output High Voltage High Drive Strength, PnDRV –3 mA, Port I/O push-pull OH I ...

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CP2400/1/2/3 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 Typical VOH ...

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Typical VOL (High Drive Mode) 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 1.5 1.2 0.9 0.6 0 Load Current (mA) ...

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CP2400/1/2/3 Table 3.3. Reset Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters RST Input High Voltage RST Input Low Voltage RST Input Pullup Current 1 V Ramp Time for Power On ...

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Pinout and Package Definitions Table 1. CP2400/1/2/3 Pin Definitions Name Pin Numbers 48-pin 32-pin SPI 2 SPI XTAL1 XTAL2 GND ...

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CP2400/1/2/3 Table 1. CP2400/1/2/3 Pin Definitions (Continued) Name Pin Numbers 48-pin 32-pin SPI 2 SPI P0 LCD2 P0 LCD3 P0 LCD4 P0.5 35 ...

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Table 1. CP2400/1/2/3 Pin Definitions (Continued) Name Pin Numbers 48-pin 32-pin SPI 2 SPI P2 — — LCD18 P2 — — LCD19 P2.0 — — COM0 P2.1 — — ...

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CP2400/1/2/3 Table 1. CP2400/1/2/3 Pin Definitions (Continued) Name Pin Numbers 48-pin 32-pin SPI 2 SPI P3 — — LCD30 P3 — — LCD31 P4 — — COM0 P4.1 7 ...

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XTAL1 1 XTAL2 2 VDD 3 GND 4 P4.3/COM3 5 CP2400 - GQ P4.2/COM2 6 Top View P4.1/COM1 7 P4.0/COM0 8 P3.7/LCD31 9 P3.6/LCD30 10 P3.5/LCD29 11 P3.4/LCD28 12 Figure 4.1. CP2400-GQ Pinout (SPI Interface) XTAL1 1 XTAL2 2 VDD ...

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CP2400/1/2/3 XTAL1 1 2 XTAL2 3 VDD GND 4 P4.3/COM 3 5 P4.2/COM 2 6 P4.1/COM 1 7 P4.0/COM 0 8 P3.7/LCD31 9 P3.6/LCD30 10 P3.5/LCD29 11 P3.4/LCD28 12 Figure 4.3. CP2400-GM Pinout (SPI Interface) XTAL1 1 2 XTAL2 3 ...

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XTAL1 1 XTAL2 2 VDD 3 CP2402 - GM GND 4 Top View P2.3/COM3 5 P2.2/COM2 6 P2.1/COM1 7 GND P2.0/COM0 8 Figure 4.5. CP2402-GM Pinout (SPI Interface) 1 XTAL1 2 XTAL2 3 VDD CP2403 - GM 4 GND Top ...

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CP2400/1/2/3 Figure 4.7. QFN-48 Package Drawing 24 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VKKD-4 except for features D2 ...

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Figure 4.8. QFN-48 Landing Diagram CP2400/1/2/3 Rev. 1.0 25 ...

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CP2400/1/2/3 Dimension Notes: General 3. All dimensions shown are in millimeters (mm) unless otherwise noted. 4. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 5. This Land Pattern Design is based on ...

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Figure 4.9. TQFP-48 Package Diagram Table 4.2. TQFP-48 Package Dimensions Dimension aaa bbb ccc ddd  Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...

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CP2400/1/2/3 Figure 4.10. TQFP-48 Recommended PCB Land Pattern Table 4.3. TQFP-48 PCB Land Pattern Dimensions Dimension Notes: General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is ...

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Figure 4.11. QFN-32 Package Drawing Table 4.4. QFN-32 Package Dimensions Dimension Min Typ Max A 0.80 0.9 1.00 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 5.00 BSC D2 3.20 3.30 3.40 e 0.50 BSC E 5.00 BSC Notes: ...

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CP2400/1/2/3 Figure 4.12. Typical QFN-32 Landing Diagram 30 Rev. 1.0 ...

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Table 4.5. PCB Land Pattern Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern ...

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CP2400/1/2/3 5. Clocking Options CP2400/1/2/3 devices include a 20 MHz internal oscillator that is selected as the system clock source upon reset. Additional clocking options include an external CMOS clock input, the internal oscillator divided ...

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SFR Definition 5.2. IOSCCN: Internal Oscillator Control Bit 7 6 Name Type R/W R/W Reset 0 0 Internal Register Address = 0x33 Bit Name 7:4 Unused Read = 00000. Write = Don’t Care. 3 Reserved Read = 0. Write = ...

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CP2400/1/2/3 6. Internal Registers and Memory The CP2400/1/2/3 is controlled by internal registers and provides the system with up to 256 bytes of additional RAM. The internal registers and memory are controlled through an indirect interface accessible through a 4-wire ...

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Accessing Internal Registers and RAM over the SPI Interface The SPI interface supports 6 commands which provide access to all internal registers and RAM. The six commands are listed in Table 6.1. Detailed information on the SPI interface including ...

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CP2400/1/2/3 6.2. Accessing Internal Registers and RAM over the SMBus Interface The SMBus interface supports 6 commands which provide access to all internal registers and RAM. The six commands are listed in Table 6.2. Detailed information on the SMBus interface ...

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Internal Registers The CP2400/1/2/3 internal registers are grouped into categories based on function. The memory map is organized to minimize register access time, by sequentially locating registers that can be read or written with a single block read or ...

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CP2400/1/2/3 Table 6.3. Internal Register Memory Map (Continued) Register Address ULPMEM03 0x84 ULP Memory Byte 3 ULPMEM04 0x85 ULP Memory Byte 4 ULPMEM05 0x86 ULP Memory Byte 5 ULPMEM06 0x87 ULP Memory Byte 6 ULPMEM07 0x88 ULP Memory Byte 7 ...

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Table 6.3. Internal Register Memory Map (Continued) Register Address P4MDO 0xBE Port 4 Output Mode P0DRIVE 0xBF Port 0 Drive Strength P1DRIVE 0xC0 Port 1 Drive Strength P2DRIVE 0xC1 Port 2 Drive Strength P3DRIVE 0xC2 Port 3 Drive Strength P4DRIVE ...

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CP2400/1/2/3 7. Interrupt Sources The CP2400/1/2/3 can alert the host processor when any of the interrupt source events listed in Table 7.1 triggers an interrupt. The CP2400/1/2/3 alerts the host of pending interrupt events by setting the appropriate flags in ...

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SFR Definition 7.1. INT0: Interrupt Status Register 0 (Self-Clearing) Bit 7 6 Name Type R R Reset 0 0 Address = 0x43 Bit Name 7:6 Unused Read = 00b. 5 Reserved Read = 0. 4 ALRM SmaRTClock Alarm Interrupt Flag. ...

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CP2400/1/2/3 SFR Definition 7.2. INT0RD: Interrupt Status Register 0 (Read-Only) Bit 7 6 Name Type R R Reset 0 0 Address = 0x40 Bit Name 7:6 Unused Read = 00b. 5 Reserved Read = 0. 4 ALRMR SmaRTClock Alarm Interrupt ...

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SFR Definition 7.3. INT0EN: Interrupt Enable Register 0 Bit 7 6 Name Type R/W R/W Reset 1 1 Address = 0x30 Bit Name 7:6 Unused Read = 11b. Write = don’t care. 5 Reserved Read = varies. Write = must ...

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CP2400/1/2/3 SFR Definition 7.4. INT1: Interrupt Status Register 1 (Self-Clearing) Bit 7 6 Name Type R R Reset 0 0 Address = 0x44 Bit Name 7:5 Unused Read = 000b. 4 RSTC Reset Complete Interrupt Flag. 0: Device has not ...

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SFR Definition 7.5. INT1RD: Interrupt Status Register 1 (Read-Only) Bit 7 6 Name Type R R Reset 0 0 Address = 0x41 Bit Name 7:5 Unused Read = 000b. 4 RSTCR Reset Complete Interrupt Flag. 0: Device has not yet ...

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CP2400/1/2/3 SFR Definition 7.6. INT1EN: Interrupt Enable Register 1 Bit 7 6 Name Type R/W R/W Reset 1 1 Address = 0x31 Bit Name 7:5 Unused Read = 111. Write = don’t care. 4 ERSTC Enable Reset Complete Interrupt. 0: ...

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Reset Sources Reset circuitry allows the CP2400/1/2 easily placed in a predefined default condition. Upon entry to this reset state, the following events occur:  All direct and indirect registers are initialized to their defined reset values. ...

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CP2400/1/2/3 8.2. Power-On Reset During power-up, the CP2400/1/2/3 is held in the reset state until V occurs between the time V reaches V DD the Electrical Characteristics of the power-on reset circuit. V RST 1.0 /RST Logic HIGH Logic LOW ...

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Power Modes The CP2400/1/2/3 has four power modes that can be used to minimize overall system power consumption. The power modes vary in device functionality and wake-up methods. Each of the following power modes is explained in the following ...

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CP2400/1/2/3 9.1. Normal Mode Normal mode should be used whenever the host controller is communicating with the CP2400/1/2/3. In this mode, the device is fully functional and the host interface is capable of operating at full speed. Typical normal mode ...

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Ultra Low Power LCD Mode In Ultra Low Power LCD Mode, the on-chip LDO is placed in a low power state and power is gated off from all digital logic residing outside the ULP block. The ULP block allows ...

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CP2400/1/2/3 9.4. Ultra Low Power SmaRTClock Mode In Ultra Low Power SmaRTClock Mode, the on-chip LDO is placed in a low power state and power is gated off from all digital logic residing outside the ULP block. LCD functionality is ...

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Shutdown Mode Shutdown mode is the lowest power mode for the CP2400/1/2/3. All device functionality is disabled in this mode and a reset is required to wake up the device. This mode is typically used when the device is ...

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CP2400/1/2/3 SFR Definition 9.1. ULPCN: Ultra Low Power Control Register Bit 7 6 Name Type R/W R/W Reset 0 0 Address = 0xA2 Bit Name 7:5 Unused Read = 000b. Write = Don’t Care. 4 RTCDIS Ultra Low Power Mode ...

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Determining the ULP Mode Wake-Up Source After waking from ULP Mode, the ULPST register may be used to determine the cause of wake up. The three pos- sible wake up sources are SmaRTClock Alarm, SmaRTClock Oscillator Failure, and ULP ...

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CP2400/1/2/3 9.7. Port Match Functionality in the Ultra Low Power Modes The ultra low power LCD and SmaRTClock modes support port match wake-up. ULP SmaRTClock mode supports port match on all P0, P1, P2, and P3 pins. ULP LCD mode ...

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SFR Definition 9.3. ULPMEMn: ULP Memory Bit 7 6 Name Type R/W R/W Reset 0 0 Addresses: ULPMEM00 = 0x81, ULPMEM01 = 0x82, ULPMEM02 = 0x83, ULPMEM03 = 0x84, ULPMEM04 = 0x85, ULPMEM05 = 0x86, ULPMEM06 = 0x87, ULPMEM07 = ...

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CP2400/1/2/3 9.8. Disabling Secondary Device Functions The MSCN and MSCF registers provide additional ways of saving power by disabling unnecessary functionality. SFR Definition 9.4. MSCN: Master Control Register Bit 7 6 Name RTCBYP CLEAR ADRINV Type R/W R/W Reset 0 ...

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SFR Definition 9.5. MSCF: Master Configuration Register Bit 7 6 Name BGMD[1:0] Reserved Type R/W R/W Reset 0 0 Address = 0xA1 Bit Name 7:6 BGMD[1:0] Band Gap Power Mode. 00: Band Gap is in Normal Power Mode. 01: Reserved. ...

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CP2400/1/2/3 10. Port Input/Output CP2400/1/2/3 devices have 36 (48-pin packages (32-pin packages) multi-function I/O pins. Port pins are organized as byte-wide ports and may be used for general purpose I/O, generating a Port Match interrupt, or for an ...

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Port I/O Modes of Operation All port pins use the Port I/O cell shown in Figure 10.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDI registers. On reset or ...

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CP2400/1/2/3 10.1.3. Interfacing Port I and 3.3 V Logic All Port I/Os configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than 4.5 V and less than 5.25 ...

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Active Mode Port Match Port match functionality allows system events to be triggered by a logic value change on a GPIO pin. A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of ...

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CP2400/1/2/3 SFR Definition 10.2. PnMSK: Port n Mask Register Bit 7 6 Name Type 0 0 Reset Address: P0MSK = 0xC9; P1MSK = 0xCA; P2MSK = 0xCB; P3MSK = 0xCC; P4MSK = 0xCD Bit Name 7:0 PnMSK[7:0] Port n Mask ...

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Registers for Accessing and Configuring Port I/O All Port I/O are accessed and configured through registers. When writing to a Port, the value written to the PnOUT register is latched to maintain the output data value at each pin. ...

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CP2400/1/2/3 SFR Definition 10.4. PnOUT: Port n Output Latch Bit 7 6 Name Type 1 1 Reset Address: P0OUT = 0xB0; P1OUT = 0xB1; P2OUT = 0xB2; P3OUT = 0xB3; P4OUT = 0xB4 Bit Name 7:0 PnOUT[7:0] Port n Output ...

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SFR Definition 10.6. PnMDI: Port n Input Mode Bit 7 6 Name Type 1 1 Reset Address: P0MDI = 0xB5; P1MDI = 0xB6; P2MDI = 0xB7; P3MDI = 0xB8; P4MDI = 0xB9 Bit Name 7:0 PnMDI[7:0] Pn Analog Configuration Bits. ...

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CP2400/1/2/3 SFR Definition 10.8. PnDRIVE: Port n Drive Strength Bit 7 6 Name Type 0 0 Reset Address: P0DRIVE = 0xBF; P1DRIVE = 0xC0; P2DRIVE = 0xC1; P3DRIVE = 0xC2; P4DRIVE = 0xC3 Bit Name 7:0 PnDRIVE[7:0] Pn Drive Strength ...

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SmaRTClock (Real Time Clock) CP2400/1/2/3 devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with alarm. The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a crystal. No ...

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CP2400/1/2/3 11.1. SmaRTClock Interface The SmaRTClock Interface consists of three registers: RTCKEY, RTCADR, and RTCDAT. These interface registers are located on the CP2400/1/2/3 register map and provide access to the SmaRTClock internal registers listed in Table 11.1. The SmaRTClock internal ...

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Using RTCADR and RTCDAT to Access SmaRTClock Internal Registers The SmaRTClock internal registers can be read and written using RTCADR and RTCDAT. The RTCADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or writes. ...

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CP2400/1/2/3 SFR Definition 11.1. RTCKEY: SmaRTClock Lock and Key Bit 7 6 Name Type Reset 0 0 Address = 0x0A Bit Name 7:0 RTC0ST SmaRTClock Interface Lock/Key and Status. Locks/unlocks the SmaRTClock interface when written. Provides lock status when read. ...

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SFR Definition 11.2. RTCADR: SmaRTClock Address Bit 7 6 Name BUSY AUTORD Type R/W R/W Reset 0 0 Address = 0x0B Bit Name 7 BUSY SmaRTClock Interface Busy Indicator. Indicates SmaRTClock interface status. Writing 1 to this bit initiates an ...

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CP2400/1/2/3 11.2. SmaRTClock Clocking Sources The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The SmaRTClock timebase is derived from the SmaRTClock oscillator circuit, which has two modes of operation: crystal mode, and self-oscillate mode. ...

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Programmable Load Capacitance The programmable load capacitance has 16 values to support crystal oscillators with a wide range of recommended load capacitance. If Automatic Load Capacitance Stepping is enabled, the crystal load capacitors start at the smallest setting to ...

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CP2400/1/2/3 11.2.4. Automatic Gain Control and SmaRTClock Bias Doubling Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects when the ...

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Missing SmaRTClock Detector The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN. When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if SmaRTClock oscillator remains high or low ...

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CP2400/1/2/3 1. Disable SmaRTClock Alarm Events (RTC0AEN = 0). 2. Set the ALARMn registers to the desired value. 3. Enable SmaRTClock Alarm Events (RTC0AEN = 1). Notes: The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is ...

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Internal Register Definition 11.4. RTC0CN: SmaRTClock Control Bit 7 6 Name RTC0EN MCLKEN Type R/W R/W Reset 0 0 SmaRTClock Address = 0x04 Bit Name 7 RTC0EN SmaRTClock Enable. Enables/disables the SmaRTClock oscillator and associated bias currents. 0: SmaRTClock oscillator ...

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CP2400/1/2/3 Internal Register Definition 11.5. RTC0XCN: SmaRTClock Oscillator Control Bit 7 6 Name AGCEN XMODE Type R/W R/W Reset 0 0 SmaRTClock Address = 0x05 Bit Name 7 AGCEN SmaRTClock Oscillator Automatic Gain Control (AGC) Enable. 0: AGC disabled. 1: ...

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Internal Register Definition 11.6. RTC0XCF: SmaRTClock Oscillator Configuration Bit 7 6 Name AUTOSTP LOADRDY Type R/W R Reset 0 0 SmaRTClock Address = 0x06 Bit Name 7 AUTOSTP Automatic Load Capacitance Stepping Enable. Enables/disables automatic load capacitance stepping. 0: Load ...

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CP2400/1/2/3 Internal Register Definition 11.7. CAPTUREn: SmaRTClock Timer Capture Bit 7 6 Name Type R/W R/W Reset 0 0 SmaRTClock AddressCAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02; CAPTURE3: 0x03. Bit Name 7:0 CAPTURE[31:0] SmaRTClock Timer Capture. These 4 registers ...

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LCD Segment Driver CP2400/1/2/3 devices contain an LCD segment driver and on-chip bias generation that supports static, 2-mux, 3- mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output voltage allows software contrast ...

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CP2400/1/2/3 12.2. LCD Configuration The LCD segment driver supports multiple mux options: static, 2-mux, 3-mux, and 4-mux mode. It also supports 1/2 and 1/3 bias options. The desired mux mode and bias is configured through the LCD0CN register. SFR Definition ...

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LCD Bias Generation and Contrast Adjustment The LCD Bias voltages are generated using the on-chip charge pump with programmable output voltage. The programmable output voltage allows software contrast control steps from 2.6 to 3.44 V. The ...

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CP2400/1/2/3 SFR Definition 12.3. LCD0CF: LCD Configuration Bit 7 6 Name Reserved Type R/W Reset 1 0 Address = 0x97 Bit Name 7:4 Reserved Read = 10b. Must Write 10b. 5:0 CPCYC[5:0] Charge Pump Cycle Period. The number of SmaRTClock ...

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LCD Timing Generation All LCD timing is derived from the SmaRTClock oscillator divided by 2. The LCD0DIVH:LCD0DIVL registers store the prescaler for generating the LCD refresh rate. The LCD mux mode must be taken into account when determining the ...

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CP2400/1/2/3 SFR Definition 12.6. LCD0TOGR: LCD Toggle Rate Bit 7 6 Name Type R/W R/W Reset 0 0 Address = 0x9A Bit Name 7:4 Unused Read = 0000. Write = Don’t Care. 3:0 TOGR[3:0] LCD Toggle Rate Divider . Sets ...

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SFR Definition 12.7. LCD0PWR: LCD0 Power Register Bit 7 6 Name Type R/W R/W Reset 0 0 Address = 0x9B Bit Name 7:5 Reserved Read = 000b. Must Write 000b. 4:3 CPCLK[1:0] Charge Pump Clock Select. 00: 1 MHz charge ...

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CP2400/1/2/3 12.5. Mapping ULP Memory to LCD Pins The ULP memory is organized in 16 bytes (32 half-bytes or nibbles), each nibble controlling 1 LCD output pin. Each LCD output pin can control LCD segments depending on ...

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Blinking LCD Segments The LCD driver supports blinking LCD applications such as clock applications where the “colon” separator toggles on and off once per second. If the LCD is only displaying the hours and minutes, then the device only ...

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CP2400/1/2/3 13. Timers CP2400/1/2/3 devices include two 16-bit auto-reload timers. These timers can be used to measure time intervals and generate periodic interrupt requests. Both timers can be clocked from the system clock source divided by 12. Timer 1 has ...

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SFR Definition 13.1. TMR0CN: Timer 0 Control Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Address = 0x54 Bit Name 7:6 Unused Read = 00b. Write = Don’t Care. 5 TF0LEN Timer 0 Low Byte Interrupt Enable. ...

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CP2400/1/2/3 SFR Definition 13.2. TMR0RLL: Timer 0 Reload Register Low Byte Bit 7 6 Name Type Reset 1 0 SFR Address = 0x50 Bit Name 7:0 TMR0RLL[7:0] Timer 0 Reload Register Low Byte. TMR0RLL holds the low byte of the ...

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SFR Definition 13.4. TMR0L: Timer 0 Low Byte Bit 7 6 Name Type Reset 0 0 SFR Address = 0x52 Bit Name 7:0 TMR0L[7:0] Timer 0 Low Byte. Contains the low byte of the 16-bit Timer 0. SFR Definition 13.5. ...

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CP2400/1/2/3 13.2. Timer 1 Timer 16-bit timer formed by two 8-bit SFRs: TMR1L (low byte) and TMR1H (high byte). Timer 1 operates in 16-bit auto-reload mode and is clocked by the system clock divided ...

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Timer 1 SmaRTClock Oscillator Capture Mode The Capture Mode in Timer 1 allows the SmaRTClock oscillator period to be measured against the system clock d by 12. Setting TF1CEN to 1 enables the SmaRTClock Oscillator Capture Mode for Timer ...

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CP2400/1/2/3 SFR Definition 13.6. TMR1CN: Timer 1 Control Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Address = 0x59 Bit Name 7:6 Unused Read = 00b. Write = Don’t Care. 5 TF1LEN Timer 1 Low Byte Interrupt ...

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SFR Definition 13.7. TMR1RLL: Timer 1 Reload Register Low Byte Bit 7 6 Name Type Reset 0 0 SFR Address = 0x55 Bit Name 7:0 TMR1RLL[7:0] Timer 1 Reload Register Low Byte. TMR1RLL holds the low byte of the reload ...

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CP2400/1/2/3 SFR Definition 13.9. TMR1L: Timer 1 Low Byte Bit 7 6 Name Type Reset 0 0 SFR Address = 0x57 Bit Name 7:0 TMR1L[7:0] Timer 1 Low Byte. Contains the low byte of the 16-bit Timer 1. SFR Definition ...

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Serial Peripheral Interface (SPI) CP2400/2 devices have a 4-wire Serial Peripheral Interface which provides access to the internal registers and memory. A typical connection to a SPI master is shown in Figure 14.1. Master Device GPIO Figure 14.1. SPI ...

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CP2400/1/2/3 14.2. Serial Clock Timing The clock to data relationship is shown in Figure 14.2. If the SPI master is a C8051 microcontroller, its SPI peripheral must be configured for Mode 0 communication (CKPOL = 0, CKPHA = 0). The ...

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Table 14.1. SPI Slave Timing Parameters Parameter Description T NSS Falling to First SCK Edge SE T Last SCK Edge to NSS Rising SD T NSS Falling to MISO Valid SEZ T NSS Rising to MISO High-Z SDZ T SCK ...

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CP2400/1/2/3 15. SMBus Interface The SMBus I/O interface is a two-wire, bi-directional serial bus that can be used to access the internal registers and memory on CP2401/3 devices. The SMBus is compliant with the System Management Bus Specification, version 1.1, ...

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SMBus Operation Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both ...

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CP2400/1/2/3 15.3.3. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve ...

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SFR Definition 15.1. SMBCF: SMBus Clock/Configuration Bit 7 6 Name ENSMB INH Type R/W R/W Reset 0 0 (CP2400/2) Reset 1 0 (CP2401/3) Address: 0x68 Bit Name SMBus Enable. 7 ENSMB This bit enables the SMBus interface when set to ...

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CP2400/1/2 OCUMENT HANGE IST Revision 0.2 to Revision 1.0  Updated Electrical Specifications to remove TBDs and specify min/max parameters.  Updated Reset Values for various registers.  Updated Register Description for LCD0PWR register. 108 Rev. 1.0 ...

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N : OTES CP2400/1/2/3 Rev. 1.0 109 ...

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